MSI-X Interrupt Interface

Table 1. MSI-X Interrupt External Interface Port Descriptions
Name	I/O	Width	Description
pcie0_cfg_msix_enable pcie1_cfg_msix_enable	O	4 in CPM4 1 in CPM5	Configuration Interrupt MSI-X Function Enabled These outputs reflect the setting of the MSI-X Enable bits of the MSI-X Control Register of Physical Functions 0 – 3. Note: In CPM5, only the Function 0 setting is indicated. For subsequent functions, the wrreq interface is used.
pcie0_cfg_msix_function_number pcie1_cfg_msix_function_number	I	8 in CPM4 16 in CPM5	Configuration MSI-X Initiating Function in CPM4. Indicates the Endpoint Function # initiating the MSI-X interrupt. 8'h00– 8'h03: PF 0 – PF 3 8’h04– 8’hFF: VF 0 – VF 252 Other encodings are reserved. Configuration MSI-X Initiating Function in CPM5. Indicates the Endpoint function # initiating the MSI-X transaction. 16'h0000-16'h100F is the supported range. Other encodings are reserved.
pcie0_cfg_msix_sent pcie1_cfg_msix_sent	O	1	Configuration Interrupt MSI-X Interrupt Sent The core generates a one-cycle pulse on this output to signal that an MSI-X interrupt message has been transmitted on the link. The user logic must wait for this pulse before signaling another interrupt condition to the core.
pcie0_cfg_msix_fail pcie1_cfg_msix_fail	O	1	Configuration Interrupt MSI-X Interrupt Operation Failed A one-cycle pulse on this output indicates that an MSI-X interrupt message was aborted before transmission onthe link. The user logic must retransmit the MSI-X interrupt in this case.
pcie0_cfg_msix_mask pcie1_cfg_msix_mask	O	4 in CPM4 1 in CPM5	Configuration Interrupt MSI-X Function Mask These outputs reflect the setting of the MSI-X Function Mask bits of the MSI-X Control Register of Physical Functions 0 – 3. Note: In CPM5, only the Function 0 setting is indicated. For subsequent functions, the wrreq interface is used.
pcie0_cfg_msix_vf_enable pcie1_cfg_msix_vf_enable	O	252	Configuration Interrupt MSI-X Enable from VFs These outputs reflect the setting of the MSI-X Enable bits of the MSI-X Control Register of Virtual Functions 0 – 251.
pcie0_cfg_msix_vf_mask pcie1_cfg_msix_vf_mask	O	252	Configuration Interrupt MSI-X VF Mask These outputs reflect the setting of the MSI-X Function Mask bits of the MSI-X Control Register of Virtual Functions 0 – 251.
pcie0_cfg_msix_address pcie1_cfg_msix_address	I	64	Configuration Interrupt MSI-X Address When the core is configured to support MSI-X interrupts and when the MSI-X Table is implemented in user memory, this bus is used by the user logic to communicate the address to be used to generate an MSI-X interrupt.
pcie0_cfg_msix_data pcie1_cfg_msix_data	I	32	Configuration Interrupt MSI-X Data When the core is configured to support MSI-X interrupts and when the MSI-X Table is implemented in user memory, this bus is used by the user logic to communicate the data to be used to generate an MSI-X interrupt.
pcie0_cfg_msix_int_vector pcie1_cfg_msix_int_vector	I	1	Configuration Interrupt MSI-X Data Valid The assertion of this signal by the user indicates a request from the user to send an MSI-X interrupt. The user must place the identifying information on the designated inputs before asserting this interrupt. When the MSI-X Table and Pending Bit Array are implemented in user memory, the identifying information consists of the memory address, data, and the originating Function number for the interrupt. These must be placed on the pcie(n)_cfg_msix_address[63:0], pcie(n)_cfg_msix_data[31:0], and pcie(n)_cfg_msix_function_number[7:0], respectively. The core internally registers these parameters on the 0-to-1 transition of pcie(n)_cfg_msix_int_vector. When the MSI-X Table and Pending Bit Array are implemented by the core, the identifying information consist so the originating Function number for the interrupt and the interrupt vector. These must be placed on pcie(n)_cfg_msix_function_number[7:0] and pcie(n)_cfg_msix_int_vector[31:0], respectively. Bit i of pcie(n)_cfg_msix_mint_vector[31:0] represents interrupt vector i, and only one of the bits of this bus can be set to 1 when asserting pcie(n)_cfg_msix_int_vector. After asserting an interrupt, the user logic must wait for the pcie(n)_cfg_msix_sent or pcie0_cfg_msix_fail indication from the core before asserting a new interrupt.

Table 2. MSI-X Interrupt Internal Interface Port Descriptions
Name	I/O	Width	Description
pcie0_cfg_msix_mint_vector pcie1_cfg_msix_mint_vector	I	32	Configuration Interrupt MSI-X Vector for CPM4 When configured in the Endpoint mode to support MSI-X interrupts, these inputs are used to signal the 32 distinct interrupt conditions associated with a PCI Function (Physical or Virtual) from the user logic to the core. The Function number must be specified on the input pcie(n)_cfg_msix_function_number. After placing the Function number on the input pcie(n)_cfg_msix_function_number, the user logic must activate one of these signals for one cycle to transmit an interrupt. The user logic must not activate more than one of the 32 interrupt inputs in the same cycle. The core internally registers the interrupt condition on the 0-to-1 transition of any bit in pcie(n)_cfg_msix_mint_vector. After asserting an interrupt, the user logic must wait for the pcie0_cfg_msix_sent or pcie0_cfg_msix_fail indication. Configuration Interrupt MSI-X Vector for CPM5 When configured in the Endpoint mode to support MSI-X interrupts, these inputs are used to signal the vector number associated with the interrupt associated with a PCI Function (Physical or Virtual) from the user logic to the core. The Function number must be specified on the input pcie(n)_cfg_msix_function_number. After placing the Function number on the input pcie(n)_cfg_msix_function_number, the user logic must activate the required vector number on this input. The core internally registers the vector number pcie(n)_cfg_msix_mint_vector qualified with pcie(n)_cfg_msix_int_vector. After asserting an interrupt, the user logic must wait for the pcie0_cfg_msix_sent or pcie0_cfg_msix_fail indication.
pcie0_cfg_msix_function_number pcie1_cfg_msix_function_number	I	8 for CPM4 16 for CPM5	For CPM4 Configuration MSI-X Initiating Function Indicates the Endpoint Function # initiating the MSI-X interrupt. 8'h00– 8'h03: PF 0 – PF 3 8’h04– 8’hFF: VF 0 – VF 252 Other encodings are reserved. For CPM4 Configuration MSI-X Initiating Function Indicates the Endpoint Function # initiating the MSI-X interrupt. 16'h00– 8'h0F: PF 0 – PF 15 16’h10– 16’hFFF: VF 0 – VF 4080 Other encodings are reserved.
pcie0_cfg_msix_sent	O	1	Configuration Interrupt MSI-X Interrupt Sent The core generates a one-cycle pulse on this output to signal that an MSI-X interrupt message has been transmitted on the link. The user logic must wait for this pulse before signaling another interrupt condition to the core.
pcie0_cfg_msix_fail	O	1	Configuration Interrupt MSI-X Interrupt Operation Failed A one-cycle pulse on this output indicates that an MSI-X interrupt message was aborted before transmission on the link. The user logic must retransmit the MSI-X interrupt in this case.
pcie0_cfg_msix_int_vector pcie1_cfg_msix_int_vector	I	1	Configuration Interrupt MSI-X Data Valid The assertion of this signal by the user indicates a request from the user to send an MSI-X interrupt. The user must place the identifying information on the designated inputs before asserting this interrupt. When the MSI-X Table and Pending Bit Array are implemented in user memory, the identifying information consists of the memory address, data, and the originating Function number for the interrupt. These must be placed on the pcie(n)_cfg_msix_address[63:0], pcie(n)_cfg_msix_data[31:0], and pcie(n)_cfg_msix_function_number[7:0], respectively. The core internally registers these parameters on the 0-to-1 transition of pcie(n)_cfg_msix_int_vector. When the MSI-X Table and Pending Bit Array are implemented by the core, the identifying information consist so the originating Function number for the interrupt and the interrupt vector. These must be placed on pcie(n)_cfg_msix_function_number[7:0] and pcie(n)_cfg_msix_int_vector[31:0], respectively. Bit i of pcie(n)_cfg_msix_mint_vector[31:0] represents interrupt vectori, and only one of the bits of this bus can be set to 1 when asserting pcie(n)_cfg_msix_int_vector. After asserting an interrupt, the user logic must wait for the pcie(n)_cfg_msix_sent or pcie0_cfg_msix_fail indication from the core before asserting a new interrupt.
pcie0_cfg_msix_enable pcie1_cfg_msix_enable	O	4	Configuration Interrupt MSI-X Function Enabled These outputs reflect the setting of the MSI-X Enable bits of the MSI-X Control Register of Physical Functions 0 – 3.
pcie0_cfg_msix_mask pcie1_cfg_msix_mask	O	4	Configuration Interrupt MSI-X Function Mask These outputs reflect the setting of the MSI-X Function Mask bits of the MSI-X Control Register of Physical Functions 0 – 3.
pcie0_cfg_msix_vf_enable pcie1_cfg_msix_vf_enable	O	252	Configuration Interrupt MSI-X Enable from VFs These outputs reflect the setting of the MSI-X Enable bits of the MSI-X Control Register of Virtual Functions 0 – 251. Note: Port not used in CPM5, use wrreq interface.
pcie0_cfg_msix_vf_mask pcie1_cfg_msix_vf_mask	O	252	Configuration Interrupt MSI-X VF Mask These outputs reflect the setting of the MSI-X Function Mask bits of the MSI-X Control Register of Virtual Functions 0 – 251. Note: Port not used in CPM5, use wrreq interface.
pcie0_cfg_msix_vec_pending pcie1_cfg_msix_vec_pending	I	2	Configuration Interrupt MSI-X Pending Bit Query/Clear These mode bits are used only when the core is configured to include the MSI-X Table and Pending Bit Array. These two bits are set when asserting pcie(n)_cfg_msix_int_vector to send an MSI-X interrupt, to perform certain actions on the MSI-X Pending Bit associated with the selected Function and interrupt vector. The various modes are: 00b: Normal interrupt generation. If the Mask bit associated with the vector was 0 when pcie(n)_cfg_msix_int_vector was asserted, the core transmits the MSI-X request TLP on the link. If the Mask bit was 1, the core does not immediately send the interrupt, but instead sets the Pending Bit associated with the interrupt vector in its MSI-X Pending Bit Array (and subsequently transmits the MSI-X request TLP when the Mask clears). In both cases, the core asserts pcie(n)_cfg_msix_sent for one cycle to indicate that the interrupt request was accepted. The user can distinguish these two cases by sampling the pcie(n)_cfg_msix_vec_pending_status output,which reflects the current setting of the MSI-X Pending Bit corresponding to the interrupt vector. 01b: Pending Bit Query. In this mode, the core treats the assertion of one of the bits of pcie(n)_cfg_msix_mint_vector as a query for the status of its Pending Bit. The user must also place the Function number of the Pending Bit being queried on the pcie(n)_cfg_msix_function_number input. The core does not transmit a MSI-X request in response, but asserts pcie(n)_cfg_msix_sent for one cycle, along with the status of the MSI-X Pending Bit on the pcie(n)_cfg_msix_vec_pending_status output. 10b: Pending Bit Clear. In this mode, the core treats the assertion of one of the bits of pcie(n)_cfg_msix_int_vector as a request to clear its Pending Bit. The user must also place the Function number of the Pending Bit being queried on the pcie(n)_cfg_msix_function_number input. The core does not transmit a MSI-X request in response, but clears he MSI-X Pending Bit of the vector (if it is set), and activates pcie(n)_cfg_msix_sent for one cycle as the acknowledgment. The core also provides the previous state of the MSI-X Pending Bit on the pcie(n)_cfg_msix_vec_pending_status output, which can be sampled by the user to determine if the Pending Bit was cleared by the core before the user request (because the pending interrupt was actually transmitted). This mode can be used to implement a polling mode for MSI-X interrupts, where the interrupt is permanently masked and the software polls the Pending Bit to detect and service the interrupt. After each interrupt is serviced, the Pending Bit can be cleared through this interface.
pcie0_cfg_msix_vec_pending_status	O	1	Configuration Interrupt MSI-X Pending Bit Status This output provides the status of the Pending Bit associated with an MSI-X interrupt, in response to query using the pcie(n)_cfg_msix_vec_pending input. It is active only when the core is configured to include the MSI-X Table and Pending Bit Array.
pcie0_cfg_msix_attr pcie1_cfg_msix_attr	I	3	Configuration Interrupt MSI/MSI-X TLP Attribute These bits enable you to set the Attribute bits that are used for both MSI and MSI-X interrupt requests. Bit 0 is the No Snoop bit. Bit 1 is the Relaxed Ordering bit. Bit 2 is the ID-Based Ordering bit. The core samples these bits on a 0-to-1 transition on pcie(n)_cfg_msi_mint_vector bits (when using MSI) or pcie(n)_cfg_msix_int_vector (when using MSI-X).
pcie0_cfg_msix_tph_present pcie1_cfg_msix_tph_present	I	1	Configuration Interrupt MSI/MSI-X TPH Present Indicates the presence of an optional Transaction Processing Hint (TPH) in the MSI/MSI-X interrupt request. The user application must set this bit while asserting pcie(n)_cfg_msi_mint_vector bits (when using MSI), or pcie(n)_cfg_msix_int_vector (when using MSI-X), if it is including a TPH in the MSI or MSI-X transaction. Note: These bits are reserved.
pcie0_cfg_msix_tph_type pcie1_cfg_msix_tph_type	I	2	Configuration Interrupt MSI/MSI-X TPH Type When pcie(n)_cfg_msix_tph_present is 1'b1, these two bits are used to supply the 2-bit type associated with the Hint. The core samples these bits on 0-to-1 transition on any bit of pcie(n)_cfg_msi_mint_vector or pcie(n)_cfg_msix_int_vector, depending on whether MSI or MSI-X interrupts are being used. Note: These bits are reserved.
pcie0_cfg_msix_tph_st_tag pcie1_cfg_msix_tph_st_tag	I	8	Configuration Interrupt MSI/MSI-X TPH Steering Tag When pcie(n)_cfg_msix_tph_present is asserted, the SteeringTag associated with the Hint must be placed on pcie(n)_cfg_msi_tph_st_tag[7:0]. The core samples these bits on 0-to-1 transition on any bit of pcie(n)_cfg_msi_mint_vector or pcie(n)_cfg_msix_int_vector, depending on whether MSI or MSI-X interrupts are being used. Note: These bits are reserved.

MSI-X Interrupt Interface - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)