Preparing Design - 3.4 English

• Generate CPM design to your specification and connect all the required interconnect or interfaces in your design within the Vivado IP integrator (BD design) and create an HDL wrapper for it (you can use the auto-generated HDL wrapper from Vivado).
• Generate the complement (RP or EP) simulation model by creating a new Vivado IP integrator (BD design) that complements your DUT. For simplicity, it is recommended to use PCIe controller mode only in Gen3 or lower speed.
  Note: If you plan to use an existing PCIe example design from an earlier generation (for example, UltraScale+), simulation models are typically generated in Gen3x16 512-bit interface compatible only. Therefore, it is easier to generate your complement design to match this interface requirement for a simpler plug-n-play.
• If you choose to use PIPE simulation to shorten simulation time, it can be enabled by using the Enable External PIPE Interface option in the CIPS GUI as shown in the following figure:

Figure 1. Enable External PIPE Interface Option

This option exposes new interfaces called common_commands_in, common_commands_out, pipe_rx_#_sigs, and pipe_tx_#_sigs where # is your PCIe lane numbers, which provide direct connection between two PCIe PHYs without the GT transceivers. The signal mapping is shown in the following table: