Preparing Design - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English
  • Generate CPM design to your specification and connect all the required interconnect or interfaces in your design within the Vivado IP integrator (BD design) and create an HDL wrapper for it (you can use the auto-generated HDL wrapper from Vivado).
  • Generate the complement (RP or EP) simulation model by creating a new Vivado IP integrator (BD design) that complements your DUT. For simplicity, it is recommended to use PCIe controller mode only in Gen3 or lower speed.
    Note: If you plan to use an existing PCIe example design from an earlier generation (for example, UltraScale+), simulation models are typically generated in Gen3x16 512-bit interface compatible only. Therefore, it is easier to generate your complement design to match this interface requirement for a simpler plug-n-play.
  • If you choose to use PIPE simulation to shorten simulation time, it can be enabled by using the Enable External PIPE Interface option in the CIPS GUI as shown in the following figure:
Figure 1. Enable External PIPE Interface Option

This option exposes new interfaces called common_commands_in, common_commands_out, pipe_rx_#_sigs, and pipe_tx_#_sigs where # is your PCIe lane numbers, which provide direct connection between two PCIe PHYs without the GT transceivers. The signal mapping is shown in the following table:

Table 1. Common In/Out Commands and PCIe PIPE Signal Mapping
In Commands PCIE PIPE Signal Mapping Out Commands PCIE PIPE Signal Mapping
Pipe_commands_in[0] Pipe_clk_input (sync to PIPE_RX buses) Pipe_commands_out[0] Pipe_clk_output (sync to PIPE_TX buses)
Pipe_commands_in[13:1] Not used Pipe_commands_out[2:1] Pipe_tx_rate[1:0]
Pipe_commands_out[3] Pipe_tx_rcvr_det
Pipe_commands_out[6:4] Pipe_tx_margin
Pipe_commands_out[7] Pipe_tx_swing
Pipe_commands_out[8] Pipe_tx_reset
Pipe_commands_out[9] Pipe_tx_deemph
Pipe_commands_out[10] Pipe_tx_rate[2]
Pipe_commands_out[13:11] Not used
Table 2. Input/Output Transceiver Buses and PCIe PIPE Signals Mapping
In Commands PCIE PIPE Signal Mapping Out Commands PCIE PIPE Signal Mapping
Pipe_rx# _sigs[31:0] Pipe_rx#_data Pipe_tx# _sigs[31:0] Pipe_tx#_data
Pipe_rx# _sigs[33:32] Pipe_rx#_char_is_k Pipe_tx# _sigs[33:32] Pipe_tx#_char_is_k
Pipe_rx# _sigs[34] Pipe_rx#_elec_idle Pipe_tx# _sigs[34] Pipe_tx#_elec_idle
Pipe_rx# _sigs[35] Pipe_rx#_data_valid Pipe_tx# _sigs[35] Pipe_tx#_data_valid
Pipe_rx# _sigs[36] Pipe_rx#_start_block Pipe_tx# _sigs[36] Pipe_tx#_start_block
Pipe_rx# _sigs[38:37] Pipe_rx#_syncheader Pipe_tx# _sigs[38:37] Pipe_tx#_syncheader
Pipe_rx# _sigs[41:39] Not used Pipe_tx# _sigs[39] Pipe_tx#_polarity
Pipe_tx# _sigs[41:40] Pipe_tx#_powerdown
  1. # = PCIe Lane numbers (for example, 16 lanes = 0 to 15).