Basic Tab - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

The Basic page with Advanced mode selected (shown in the following figure) includes additional settings. The following parameters are visible on the Basic page when the Advanced mode is selected.

Figure 1. Basic Tab, Advanced Mode

PCIe Link Debug
This enables the link debug option to be activated.
Enable External PIPE Interface
When selected, this option enables an external third-party bus functional model (BFM) to connect to the PIPE interface of integrated block for PCIe. For details, see XAPP1184, which provides examples of using Gen2 and Gen3 cores in Endpoint configurations. Refer to these designs to connect the External PIPE Interface ports of the core to third-party BFMs.
Enable Lane Reversal
Logical lane reversal is enabled by default, it can be disabled using this option. For more details, see Lane Reversal.