This appendix provides guidance on Interrupt Request (IRQ) pins routing and programming for CPM4. AMD Versal adaptive SoC CPM Mode for PCIe provides three independent IRQ pins routed to the programmable logic (PL) region as well as three independent IRQ pins routed to the hardened processing system (PS) region. These IRQ pins are shared between the two PCIe controllers and all CPM4 use modes and can be programmed to route one or many interrupt sources.
The three IRQ pins routed to the PL region are named
cpm_misc_irq, cpm_cor_irq, and
cpm_uncor_irq and these pins are visible in the Vivado block diagram canvas on the AMD
Versal CIPS IP boundary. Although, the IRQ pins are named as
miscellaneous, correctable, and uncorrectable respectively, they function identically
from each other and have the same list of interrupt source to select from. Therefore,
you can assumes that these IRQ pins as three separate general purpose IRQ pins.
The three IRQ pins routed to the PS regions are named similarly. However, they are not visible in the Vivado block diagram canvas and they are using hardened silicon routing. These paths are always enabled and no extra customization is required during CIPS IP customization to use it. These IRQ pins also function identically and have the same list of Interrupt source to select from as the PL IRQ pins counterparts and can be used with the PL IRQ pins.
There are many interrupt sources to select from and the complete list is available in the Versal Adaptive SoC Register Reference (AM012). This appendix provides one use case example to showcase how the IRQ pins mux registers are programmed and includes firmware guidance to service the interrupt request.
Example: Generate Interrupt Request for PCIe Message Event
In this example, you generate interrupt whenever PCIe Message
TLP is received for PCIe0 and PCIe1 controller. You
route interrupt generated from PCIe0 controller to the PS region
while interrupt generated from PCIe1 controller to the PL region. You
use the cpm_misc_irq pin as an example, but any other pins can also
be used. A high level block diagram of the interrupt routing is shown in the
following diagram:
- Register programming to enable PCIe message event interrupt
- The following register is programmed by you at runtime to enable the interrupt:
- Interrupt service routine
- The following steps outline the recommended procedure to service the interrupt request: