Interrupt Request (IRQ) Routing and Programming for CPM4 - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

This appendix provides guidance on Interrupt Request (IRQ) pins routing and programming for CPM4. AMD Versal adaptive SoC CPM Mode for PCIe provides three independent IRQ pins routed to the programmable logic (PL) region as well as three independent IRQ pins routed to the hardened processing system (PS) region. These IRQ pins are shared between the two PCIe controllers and all CPM4 use modes and can be programmed to route one or many interrupt sources.

The three IRQ pins routed to the PL region are named cpm_misc_irq, cpm_cor_irq, and cpm_uncor_irq and these pins are visible in the Vivado block diagram canvas on the AMD Versal CIPS IP boundary. Although, the IRQ pins are named as miscellaneous, correctable, and uncorrectable respectively, they function identically from each other and have the same list of interrupt source to select from. Therefore, you can assumes that these IRQ pins as three separate general purpose IRQ pins.

The three IRQ pins routed to the PS regions are named similarly. However, they are not visible in the Vivado block diagram canvas and they are using hardened silicon routing. These paths are always enabled and no extra customization is required during CIPS IP customization to use it. These IRQ pins also function identically and have the same list of Interrupt source to select from as the PL IRQ pins counterparts and can be used with the PL IRQ pins.

There are many interrupt sources to select from and the complete list is available in the Versal Adaptive SoC Register Reference (AM012). This appendix provides one use case example to showcase how the IRQ pins mux registers are programmed and includes firmware guidance to service the interrupt request.

Example: Generate Interrupt Request for PCIe Message Event

In this example, you generate interrupt whenever PCIe Message TLP is received for PCIE0 and PCIE1 controller. You route interrupt generated from PCIE0 controller to the PS region while interrupt generated from PCIE1 controller to the PL region. You use the cpm_misc_irq pin as an example, but any other pins can also be used. A high level block diagram of the interrupt routing is shown in the following diagram:

Figure 1. Interrupt Request (IRQ) Routing Diagram

Register programming to enable PCIe message event interrupt
The following register is programmed by you at runtime to enable the interrupt:
  • For PCIE0 controller
    • CPM_SLCR.PS_MISC_IR_ENABLE set to 0x10 to select pcie0_cfg_msg_received
    • Read to confirm that CPM_SLCR.PS_MISC_IR_MASK is cleared for bit[4] pcie0_cfg_msg_received
  • For PCIE1 controller
    1. CPM_SLCR.PL_MISC_IR_ENABLE set to 0x20 to select pcie1_cfg_msg_received
    2. Read to confirm that CPM_SLCR.PL_MISC_IR_MASK is cleared for bit[5] pcie1_cfg_msg_received
Interrupt service routine
The following steps outline the recommended procedure to service the interrupt request:
  • For PCIE0 controller:
    • Upon receiving interrupt, read CPM_SLCR.PS_MISC_IR_STATUS to confirm bit[4] pcie0_cfg_msg_received is asserted
    • CPM_SLCR.PS_MISC_IR_DISABLE set to 0x10 to temporarily mask "pcie0_cfg_msg_received" so further interrupt is not received while existing interrupt is being serviced
    • Execute user-defined task for servicing PCIe Message event.
    • CPM_SLCR.PS_MISC_IR_STATUS set to 0x10 to clear "pcie0_cfg_msg_received"
    • Re-enable / unmask PCIe Message event interrupt source by programming the CPM_SLCR.PS_MISC_IR_ENABLE register
  • For PCIE1 controller:
    • Upon receiving interrupt, read CPM_SLCR.PL_MISC_IR_STATUS to confirm bit[5] pcie1_cfg_msg_received is asserted
    • CPM_SLCR.PL_MISC_IR_DISABLE set to 0x20 to temporarily mask pcie1_cfg_msg_received so further interrupt is not received while existing interrupt is being serviced
    • Execute user-defined task for servicing PCIe message event.
    • CPM_SLCR.PL_MISC_IR_STATUS set to 0x20 to clear pcie1_cfg_msg_received
    • Re-enable / unmask PCIe Message event interrupt source by programming the CPM_SLCR.PL_MISC_IR_ENABLE register