Legacy Interrupt Interface - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English
Table 1. Legacy Interrupt Interface Port Descriptions
Name I/O Width Description
pcie0_cfg_interrupt_int pcie1_cfg_interrupt_int I 4 Configuration INTx Vector: When the core is configured as EP, these four inputs are used by the user application to signal an interrupt from any of its PCI Functions to the RC using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express. These four inputs correspond to INTA, INTB, INTC, and INTD of the PCI bus, respectively. Asserting one of these signals causes the core to send out an Assert_INTx message, and deasserting the signal causes the core to transmit a Deassert_INTx message.
pcie0_cfg_interrupt_sent pcie1_cfg_interrupt_sent O 1 Configuration INTx Sent: A pulse on this output indicates that the core has sent an INTx Assert or Deassert message in response to a change in the state of one of the pcie(n)_cfg_interrupt_int inputs.
pcie0_cfg_interrupt_pending pcie1_cfg_interrupt_pending I

4 in CPM4

16 in CPM5

Configuration INTx Interrupt Pending: Per Function indication of a pending interrupt from the user. pcie(n)_cfg_interrupt_pending[0] corresponds to Function #0. Each of these inputs is connected to the Interrupt Pending bits of the PCI Status Register of the corresponding Function.