1024-Bit Completer Interface - 3.4 English

Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346)

Document ID
PG346
Release Date
2024-05-30
Version
3.4 English

This section describes the operation of the completer interface in the user-side interfaces associated with the 1024-bit AXI4-Stream Interface.

Note: All signals in the waves are not appended with pcie0 or pcie1 ports, but apply to both pcie0* and pcie1* ports.

The completer interface maps the transactions (memory, I/O read/write, messages, and atomic operations) received from the PCIe link into transactions on the completer request interface based on the AXI4-Stream protocol. The completer interface is required to be connected to the user application in all PCIe Endpoint implementations, but it is optional for root complexes. The completer interface consists of two separate interfaces, one for data transfer in each direction. Each interface is based on the AXI4-Stream protocol, with a data width of 1024 bits. The completer request interface is for transfer of requests (with any associated payload data) to the user application, and the completer completion interface is for receiving the completion data (for a Non-Posted request) from the user application for forwarding on the link. The two interfaces operate independently. That is, the core can transfer new requests over the completer request interface while receiving a completion for a previous request.