The control interface can be used when cache coherency is not implemented or if a master not connected to one of the optimized ACE ports should handle the cache maintenance. Both Flush and Clear type of operations are available by writing to registers on the control interface. The rules for when Flush or Clear should be used are the same as for the cache coherent case.
The cache maintenance operations from the control port have lower priority than ordinary transactions from the optimized and generic ports. Due to this they can be slower than the equivalent cache coherent counterpart if the cache load remains high during cache maintenance.
When Non-Secure handling is enabled there are two separate sets of registers for Secure and Non-Secure Clear and Flush.