Core Parameters Tab - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

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5.0 English

The Core Parameters Tab is shown in the following figure.

Figure 1. Core Parameters Tab
Number of Optimized AXI4 Ports
Sets the number of optimized ports that are available to connect to a MicroBlaze processor or equivalent IP in terms of AXI4/ACE transaction support.
Number of Generic AXI4 Ports
Set the number of generic AXI4 ports that are available for IP cores not adhering to the AXI4 subset required for an optimized port, such as DMA.
Enable Slave Coherency
Set slave port cache coherency mode to None or ACE Coherency Protocol.
Enable Master Coherency
Set master port cache coherency mode to None, ACE Coherency Protocol, CCIX Coherency Protocol or CHI Coherency Protocol.
Sets the size of the system cache in bytes from 32k to 4M.
N-Way Set Associative
Specifies 2- or 4-way set associative cache.
Line Length
Set the cache line length in 32-bit words from 16 to 1024. For CCIX, CHI and ACE master coherency the cache line length is fixed to 16.
Figure 2. Core Parameters Tab with CCIX Coherency Protocol
Figure 3. Core Parameters Tab with CHI Coherency Protocol
Enable Integrity
Enable Error Correcting Codes (ECC) for the cache tag, and parity for cache data. If address translation is used, ATC parity is also enabled.