2019.2 Release
- Added AXI user signals reserved for future us
- Added Initializing output signal
2020.1 Release
- Changed default value of C_Sx_AXI_PROHIBIT_WRITE_ALLOCATE to 0
- Changed default value of C_Sx_AXI_GEN_PROHIBIT_WRITE_ALLOCATE to 0
- Added CXS interface for CCIX coherency, and related parameters
- Added AXI4-Stream interfaces for ATS address translation, and related parameters
- Added interrupt output signal
2020.2 Release
- Added CHI interface for CHI coherency, and related parameters
2024.2 Release
- Added C_ENABLE_FAST_INIT_SIM to speed up simulation by skipping initialization after reset