- Support for Cache Coherent Interconnect for Accelerators (CCIX®) Request Agent (RA) coherency protocol with one port and one link
- Support for CHI interface with one Request Node (RN)
- Address Translation Cache (ATC) with the PCIe® Address Translation Service (ATS) protocol
- Dedicated AXI4 slave ports for a MicroBlaze™ processor
- Up to 16 generic AXI4 slave ports for other AXI4 masters, limited to four ports with CCIX master coherency
- Up to 16 generic AXI4 slave ports for other AXI4 masters
- Optional cache coherency on dedicated MicroBlaze processor ports with AXI Coherency Extension (ACE)
- Optional support for exclusive access with non-coherent configuration
- Optional cache coherency on master port for Zynq® UltraScale+™ MPSoC connection
- Optional support for Non-Secure transactions
- Optional support for AXI error handling
- AXI4 master port connecting the external memory controller
- Highly configurable cache—2 or 4 set associative cache of up to 4 MB in size
- Optional AXI4-Lite Statistics and Control port
- Supports up to 64-bit AXI4 address width
- Optional support for 64-bit AXI4 Virtual Address via ATS and PRI over PCIe
- Optional support for PCIe Advanced Error reporting (AER) error handling, when ATS is in use