Revision History - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

Document ID
Release Date
5.0 English

The following table shows the revision history for this document.

Section Revision Summary
11/05/2021 Version 5.0
General Updates
  • Added support for CCIX CPM mode, Versal Premium, CXS (data width 256, 512, and 1024 bits)
  • Updated CCIX PASID support, Host TA PASID propagation, Versal Premium
  • Extended support for ATS AXIS (data width 1024 bits), Versal Premium
08/06/2021 Version 5.0
General Updates
  • Added support for PCIe 10bits TAG, requires Host Capabilities support and announcement for activation
  • Added support for Versal FunctionID/ComponetID to supersede EP BDF for self identification (None/Partial/Full)
  • Updated Port Link Tx/Rx Status with CCIX/CHI context definition and CXS/CHI Link status signal inspection
12/11/2020 Version 5.0
General Updates
  • Added optional support for CHI
  • Added optional support for ATS PASID
07/08/2020 Version 5.0
General Updates
  • Added optional support for CCIX
  • Added optional support for ATS
  • Added Interrupt port
  • Added support for snoop effect configuration
  • Added optional support for integrity in the CCIX case
10/30/2019 Version 5.0
General Updates
  • Increased supported cache size
  • Added fine-grained control over RAM utilization
  • Added Initialization port
  • Increased supported cache line lengths
04/05/2017 Version 4.0
Property Translation Added section for AXI transaction properties and translation
10/05/2016 Version 4.0
General Updates
  • Added optional support for master port cache coherency
  • Added optional support of Non-Secure transactions
  • Added optional support for AXI4 error handling
  • Added per slave port allocate and buffer override functionality
  • Updated Xilinx
11/18/2015 Version 3.1
General Updates Added support for UltraScale+™ families
06/24/2015 Version 3.1
General Updates Moved performance and resource utilization data to the web
04/01/2015 Version 3.1
General Updates
  • Increased optimized ports to 16
  • Increased generic ports to 16
  • Added support for 16 word cache line when coherent
  • Resource tables updated
  • Support of up to 64-bit address width
10/02/2013 Version 3.0
General Updates
  • Revision number advanced to 3.0 to align with core version number.
  • Description of new reset behavior
  • Resource tables updated
  • Updated latency number for write transactions
03/20/2013 Version 1.0
Initial release. Replaces PG031. No documentation changes for this release.