CHI is used for connection to local cache coherency in a device or system-wide cache coherency. System Cache provides one Request Node (RN-F) that can access the local Home Node (HN) in the Versal CPM and multiple Home Agents (HA) when CCIX is enabled externally in the CPM. Up to four AXI4 interfaces are provided per System Cache instance for accelerator connections as shown in the following figure.
System Cache connects to the CPM block with one CHI point-to-point interface and with four AXI4-Stream interfaces when ATS address translation is enabled. The CPM has two CHI ports so that two System Caches can be connected to the same CPM. An ATS switch is included to distribute ATS traffic to all System Cache instances. The FPGA is connected to other devices via PCIe, which tunnels CCIX traffic on a Virtual Channel (VC). These devices must contain one or more HAs, and may possibly even have internal RAs, as well as connect to other devices with additional RAs and/or HAs.