Enabling master port cache coherency with accelerators in the Zynq® UltraScale+™ MPSoC PL improves memory management by providing a local cache that is hardware cache coherent to the APU caches. With a correctly sized cache the majority of the accelerator AXI traffic can be terminated in the System Cache core to reduce the impact on the PS internal bandwidth. Snoop traffic generated from the PS is also handled efficiently by the System Cache core.