When the System Cache core shares the memory controller(s) with at least one other master, a back-door DMA connection is opened up. The following figure shows a configuration with one additional master. This back-door connection creates issues with data visibility; if an address is allocated in the System Cache core it hides data newly updated by the MicroBlaze™ processor from the other masters that access the memory directly, because the System Cache core uses a write-back storage policy. Similarly, updates from other masters to main memory are hidden from the MicroBlaze processor due to the system cache allocation, which provides the obsolete data that has been previously allocated.
There are multiple solutions to the issues that arise from this system design, depending on the System Cache core configuration. All methods are designed to make sure that an address is not allocated in any of the cache lines in a set.
