Property Override - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

Document ID
PG118
Release Date
2021-11-05
Version
5.0 English

To achieve the expected transaction behavior all Optimized and Generic slave ports have parameters to override the original transaction settings for all the Allocate bits and the Bufferable bit. They can be used to set the properties for AXI Masters that have non-programmable ARCACHE and/or AWCACHE configurations that do not match the desired transaction properties.

Parameters such as C_Sx_AXI_[GEN_]FORCE_[READ|WRITE]_[ALLOCATE|BUFFER] set the corresponding bit to 1, whereas parameters such as C_Sx_AXI_[GEN_]PROHIBIT_[READ|WRITE]_[ALLOCATE|BUFFER] clear the bit to 0.

The following tables show the relationship between the corresponding parameters and the ARCACHE and AWCACHE bits respectively for an Optimized port. An identical mapping applies to the Generic S_AXI_GEN ports. The Modifiable bit is not applicable.

Table 1. Parameter to ARCACHE Bit Mapping
Other Allocate Read Allocate Bufferable
C_Sx_AXI_FORCE_WRITE_ALLOCATE C_Sx_AXI_FORCE_READ_ALLOCATE C_Sx_AXI_FORCE_READ_BUFFER
C_Sx_AXI_PROHIBIT_WRITE_ALLOCATE C_Sx_AXI_PROHIBIT_READ_ALLOCATE C_Sx_AXI_PROHIBIT_READ_BUFFER
Table 2. Parameter to AWCACHE Bit Mapping
Write Allocate Other Allocate Bufferable
C_Sx_AXI_FORCE_WRITE_ALLOCATE C_Sx_AXI_FORCE_READ_ALLOCATE C_Sx_AXI_FORCE_WRITE_BUFFER
C_Sx_AXI_PROHIBIT_WRITE_ALLOCATE C_Sx_AXI_PROHIBIT_READ_ALLOCATE C_Sx_AXI_PROHIBIT_WRITE_BUFFER