CHI Example - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

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5.0 English

System Cache configured to use CHI Master Coherency enables cache coherency similar to CCIX. In this case System Cache is connected to CPM in Versal, which has the ability to extend the coherency domain to enable cache coherency with memory distributed throughout the system, all controlled by a PCIe host. In this use case the accelerators connect to System Cache using AXI4 and System Cache provides a local cache function coherent with the rest of the CHI/CCIX memory systems, without any need for the accelerators to handle the coherency protocol. CPM has the ability to connect to two System Cache cores with CHI enabled.

Figure 1. CHI Request Node (RN-F) System

In the CHI configuration up to four accelerators/kernels can be used, connected to System Cache with ordinary AXI4 interfaces. The system can be configured to use Shared Virtual Memory, SVM, via the Address Translation Services, ATS. CPM supports the ability to use PASID, which enables each accelerator to use a unique ID when requesting address translation. A MicroBlaze processor subsystem handles all the configuration and maintenance to make System Cache operate as a full member of the CHI network.

Key building blocks in this solution are:
  • Optional PCIe Host with CCIX Home Agent
  • Versal CPM for CHI connection and potential connection to CCIX domain
  • One or two System Cache cores configured as Request Node using the CHI protocol to keep the local cache coherent with the rest of the memory system, and the Address Translation Cache (ATC) to handle virtual address translation with PASID
  • MicroBlaze processor based sub-system controlling System Cache to provide configuration and control connection to rest of the system
  • Up to four accelerators connected via AXI4 to each System Cache
Figure 2. CHI Component Overview