The System Cache core has up to 16 AXI4 interfaces optimized for accesses performed by the cache interfaces on the MicroBlaze™ processor. Because the MicroBlaze processor has one AXI4 interface for the instruction cache and one for the data cache, systems with up to eight MicroBlaze processors can be fully connected.
By using a 1:1 AXI4 interconnect to directly connect the MicroBlaze processor and the System Cache core, access latency for MicroBlaze processor cache misses is reduced, which improves performance. The optimization to only handle the types of AXI4 accesses issued by the MicroBlaze processor simplifies the implementation, saving area resources as well as improving performance. The data widths of the MicroBlaze processor optimized interfaces are parameterized to match the data widths of the connected MicroBlaze processors. With wide interfaces the MicroBlaze processor cache line length normally determines the data width.
The Optimized AXI4 slave interfaces are compliant to a subset of the AXI4 interface specification. The interface includes the subsequent features and exceptions:
- Support for 32-, 128-, 256-, and 512-bit data widths
- Support for some AXI4 burst types and sizes
- No support for FIXED bursts
- WRAP bursts corresponding to the MicroBlaze processor cache line length (either 4, 8, or 16 beats)
- Single beat INCR burst, or either 4, 8, or 16 beats corresponding to the MicroBlaze processor cache line length
- Exclusive accesses are treated as a normal accesses, never returning EXOKAY, unless the internal exclusive monitor is enabled
- Optional support for Secure/Non-Secure handling
- Only support for native transaction size (same as data width for the port)
- Only support for burst transactions that are contained within a single cache line in the System Cache core
- AXI4 user signals are not supported
- All transactions executed in order regardless of thread ID value. No read reordering or write reordering is implemented.