Address Translation Service and Cache - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

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5.0 English
There are various reasons for enabling System Cache address translation, including:
  • Avoiding host device driver and letting accelerators work directly with addresses provided by the host application
  • Limiting the impact of “memory leakage” or an incorrectly programmed endpoint
  • Address space conversion (smaller endpoint address range to larger system virtual address space)
  • Providing scatter/gather functionality
  • Virtualization support

The System Cache includes an ATC function with companion ATS to support virtual address handling. The function is split into three parts:

ATC Translation Lookaside Buffer, located in each AXI4 Slave port interface, which holds the most recently used translations for AR and AW channel transactions respectively.
ATC Table
ATC Translation Lookaside Buffer Cache, one common table with recently cached local copies of the Host TA Virtual to Physical Address map, with a default size of 256 entries.
Address Translation Service, protocol based message service over PCIe Virtual Channel 0 (VC0), including message structures to support maintenance of ATC Table synchronization with the Host TA.

To enable ATS, configure System Cache with optional C_ENABLE_ADDRESS_TRANSLATION set. The ATS function is activated through the System Cache Capability registers and the PCIe configuration structure, mirrored in the System Cache register space.

If ATS is enabled, but not activated, System Cache will not issue any ATS Translation Requests and will use the “untranslated” physical addresses for all read and write requests.

If System Cache is configured with address translation disabled, the ATS AXI4-Stream interfaces are not visible on the System Cache IP core.

The System Cache translation process, using the ATC Table and the AR and AW channel ATC TLB for each of the AXI4 Slave ports provides:

  • The ability to reduce look-up latency by distributing address translation caching
  • Reduced probability of “thrashing” within the Host TA memory management entries
  • Improved system performance by ATC TLB search, ATC Table locality, and reduced dependency on the Host TA latency
  • Reduced latency by less frequent requests to the Host TA for missing address mappings

ATS uses a request-completion protocol between an endpoint, System Cache and the Host TA, to provide the translation service. ATS capabilities also include handling the Page Request Interface (PRI), to request the Host TA to map requested pages.

Because System Cache only expects ATS/PRI messages, any other messages on VC0 must be filtered out outside System Cache. Unexpected messages will be silently discarded, to avoid inconsistency or message blocking, causing data to be lost for any memory or I/O accesses.

The System Cache ATS interface consists of independent Request/Completion streams, two for Requester and two for Completer, each having programmable parity protection and checking on the AXI4-Stream interfaces.

  • Incoming Completer Request (CQ) interface through which ATS Invalidation requests and PRI Response from Host TA are sent to the System Cache
  • Outgoing Completer Completion (CC) interface through which the System Cache sends back responses to the completer requests (including AER error handling)
  • Outgoing Requester Request (RQ) interface through which the System Cache generates translation requests to the Host TA, ATS Invalidation completions and PRI requests
  • Incoming Requester Completion (RC) interface through which the translation completions are received from the Host TA in response to System Cache ATS TA requests

To allow ATC Table entries to use unique virtual address spaces, System Cache optionally allows a Process Address Space ID (PASID) extension.

With CCIX protocol address translations, using a Host TA without PASID propagation, the virtualization with the PASID extension is added to the AXI4 Slave ports to allow different processes to use dedicated translation mappings in the ATC over time, which will not propagate PASID on the AXI4-Stream interfaces.

With CHI protocol address translation and CCIX protocol address translation for supported technologies, the added PASID extension also propagates the PASID to the Host TA via the AXI4-Stream interfaces.

When Host TA PASID propagation is enabled the page attributes Privileged and Execute options are propagated from Host TA together with normal Read/Write attributes, as well as the translated page attributes Global Mapping (same TA page mapping regardless of PASID) and Global Invalidate (invalidate all TA pages in ATC table regardless of PASID for given TA).