Bandwidth - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

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5.0 English

Using wider AXI4 interfaces increases data bandwidth, but also increases FPGA resource usage. Using the widest possible common AXI4 data width between the System Cache AXI4 Master and the external memory gives the highest possible bandwidth. This also applies to the AXI4 connection between MicroBlazeâ„¢ processor caches and the System Cache core. The widest possible common width gives the highest bandwidth.