The system parameter tab for AXI, CCIX and CHI master interfaces is shown in the following figures with the data width parameters visible for the slave interface.
Figure 1. System Parameter Tab with AXI Master Interface
- M_AXI Address Width
- Sets the address width of the master interface that is connected to the memory subsystem.
- M_AXI Data Width
- Sets the data width of the master interface that is connected to the memory subsystem.
- M_AXI Thread ID Width
- Sets the ID width of the master interface that is connected to the memory subsystem.
- Sx_AXI_GEN Data Width
- Sets the data width of the generic ports individually.
Figure 2. System Parameter Tab with CCIX Master Interface
- CXS0 Flit Data Width
- Sets the data width of the CXS interface flit to 256 or 512 bits, and also 1024 bits for Versal Premium devices.
- CXS0 Packet Header
- Defines the CCIX packet header format, either Compatible or Optimized.
- CXS0 No Message Packing
- Set if only a single message is packed into each CCIX packet.
- Sx_AXI_GEN Data Width
- Sets the data width of the generic ports individually.
Figure 3. System Parameter Tab with CHI Master Interface
- M0_CHI Data Width
- Sets the data width of the CHI interface.
- Sx_AXI_GEN Data Width
- Sets the data width of the generic ports individually.