The ATS interface uses four AXI4-Stream channels: CC, CQ, RC and RQ. These channels are connected to PCIe, VC0, when used together with CCIX or CHI. The following features are supported:
- Interface width 256 or 512 bits, and also 1024 bits for Versal Premium devices, must be the same width as the CXS width with CCIX
- Either 256 or 512-bit (1024-bit for Versal Premium devices) wide interfaces can be used with the CHI, independent of the CHI data width (must be same as PCIe VC0)
- Per channel user signals are supported with CCIX on UltraScale™ and UltraScale+™ devices according to the definition in Integrated Block for PCI Express (PG213)
- Per channel user signals are supported with CHI on Versal ACAP devices according to the definition in Versal ACAP Integrated Block for PCI Express (PG343)
- Per channel user signal width, definition depends on data width and optional PASID width for CHI (Versal) and CHI/CCIX (Versal Premium)
- Burst sizes via header PCIe packet length, limited by Message type and system MPS configured by firmware in the System Cache ATS PCIe Control register
- Packet delimiter by AXI4-Stream protocol or by straddle user signals when the option is selected
- Single and Burst multibeat transactions qualified by AXI4-Stream protocol or by straddle user signals when the option is selected
- Slave side back pressure allowed
- Parity protected, per byte odd parity bit, when the option is selected
- Supports abortion and rejection of header and payload via user signals