Register Space - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

Document ID
PG118
Release Date
2021-11-05
Version
5.0 English

In the following tables Access is indicated by R for read-only, W for write-only and R/W for Read/Write.

All registers in the optional Statistics and Control module are 64 bits wide. The address map structure is shown in the following table. The data width of the control interface is configurable to be 32 (default) or 64 bits. For the 32-bit interface a write to a control-type register takes effect on the write to the lower 32-bits. For a 64-bit interface the control register write always takes effect immediately.