IP Facts - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

Document ID
Release Date
5.0 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 UltraScale+™

Virtex® UltraScale+™ HBM


Zynq®-7000 SoC

Zynq® UltraScale+™ MPSoC

7 series


Supported User Interfaces AXI4, ACE, AXI4-Lite, AXI4-Stream (ATS), CXS (CCIX), CHI
Resources Performance and Resource Use web page
Provided with Core
Design Files Vivado® RTL
Example Design See the CCIX lounge and the Versal CCIX lounge (registration required)
Test Bench Not Provided
Constraints File Not Provided
Simulation Model Not Provided
Supported S/W Driver N/A
Tested Design Flows
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Release Notes and Known Issues Master Answer Record: 54452
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Provided by Xilinx at the Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.