Backend CCIX and CHI Registers - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)
Document ID
PG118
Release Date
2021-11-05
Version
5.0 English

Backend CCIX and CHI Registers

In the nominal use case the registers below are handled by firmware executing in the MicroBlaze processor sub-system, and there is nothing the user needs to handle.

Fields denoted with FW: in the descriptions below are updated by the firmware.

Unused CCIX registers are reserved in CHI context, and will return Reserved default value if read.

Table 1. Backend CCIX Address Map
Offset Register Name Access Format Description
0x1_A200 CCIXCCSI0 R 32 Primary Port 0 Common Capability & Status I
0x1_A204 CCIXCCSII0 R 32 Primary Port 0 Common Capability & Status II
0x1_A208 CCIXCCSIII0 R 32 Primary Port 0 Common Capability & Status III
0x1_A210 CCIXCCI0 R/W 32 Primary Port 0 Common Control I
0x1_A214 CCIXCCII0 R/W 32 Primary Port 0 Common Control II
0x1_A218 CCIXDEVECS0 R/W 32 CCIX Device Error Control & Status
0x1_A21C CCIXSCPCIE0 R/W 32 Primary Port 0 SC PCIe & CCIX Common
0x1_A280 CCIXCSI0 R 32 Port 0 Capability & Status I
0x1_A284 CCIXCSII0 R 32 Port 0 Capability & Status II
0x1_A288 CCIXCSIII0 R 32 Port 0 Capability & Status III
0x1_A290 CCIXCS00 R 32 Port 0 Error Control & Status 0
0x1_A294 CCIXCS10 R 32 Port 0 Error Control & Status 1
0x1_A298 CCIXCI0 R/W 32 Port 0 Control I
0x1_A29C CCIXTPIDM0 R/W 32 Port 0 Source TransportID Map
0x1_A300 CCIXL0TXS0 R 64 Port 0 Link 0 System Cache Tx Status
0x1_A380 CCIXL0RXS0 R 64 Port 0 Link 0 System Cache Rx Status
0x1_A680 CCIXL0BFCV0 R/W 64 Port 0 Link 0 BFCV0 + BFCV1
0x1_B000 CCIXL0CI0 R/W 32 Port 0 Link 0 Control I
0x1_B004 CCIXL0CII0 R/W 32 Port 0 Link 0 Control II
0x1_B008 CCIXL0CIII0 R/W 32 Port 0 Link 0 Control III
0x1_B00C CCIXL0CIV0 R/W 32 Port 0 Link 0 Control IV
0x1_B010 CCIXL0ECS00 R/W 32 Port 0 Link 0 Error Control & Status 0
0x1_B014 CCIXL0ECS01 R/W 32 Port 0 Link 0 Error Control & Status 1
0x1_B018 CCIXL0DTPIDM0 R/W 32 Port 0 Link 0 Destination TransportID Map
0x1_B01C CCIXL0PLSPEC0 R/W 32 Port 0 Link 0 SC Port/Link Specific
0x1_B200 CCIXLCSI0 R 32 Port 0 Link Capability and Status I
0x1_B204 CCIXLCSII0 R 32 Port 0 Link Capability and Status II
0x1_B208 CCIXLCSIII0 R 32 Port 0 Link Capability and Status III
0x1_B20C CCIXLCSIV R 32 Port 0 Link Capability and Status IV
0x1_B300 CCIXTRA0CS1 R 32 RA0 Capability and Status 1
0x1_B304 CCIXRA0CI R/W 32 RA0 Control I
0x1_B310 CCIXRA0ECS0 R/W 32 RA0 Error Control & Status 0
0x1_B314 CCIXRA0ECS1 R/W 32 RA0 Error Control & Status 1
0x1_B318 CCIXRA0SCSPE R/W 64 SC RA0 Specific
Table 2. Backend CHI Address Map
Offset Register Name Access Format Description
0x1_A300 CCIXL0TXS0 R 64 Port 0 Link 0 System Cache Tx Status
0x1_A380 CCIXL0RXS0 R 64 Port 0 Link 0 System Cache Rx Status
0x1_B01C CCIXL0PLSPEC0 R/W 32 Port 0 Link 0 SC Port/Link Specific
0x1_B300 CCIXTRA0CS1 R 32 RA0 Capability and Status 1
0x1_B304 CCIXRA0CI R/W 32 RA0 Control I
0x1_B310 CCIXRA0ECS0 R/W 32 RA0 Error Control & Status 0
0x1_B314 CCIXRA0ECS1 R/W 32 RA0 Error Control & Status 1
0x1_B318 CCIXRA0SCSPE R/W 64 SC RA0 Specific

Primary Common Capabilities & Status I (DVSEC) Register

Figure 1. Primary Common Capabilities & Status I (DVSEC) Register System Cache Page-1 Sheet.95 Sheet.71 Sheet.65 Sheet.8 Sheet.3 0 0 Sheet.7 Sheet.9 2 2 Sheet.12 3 3 Sheet.40 Sheet.66 21 21 Sheet.69 22 22 Sheet.72 23 23 Sheet.73 Sheet.75 24 24 Sheet.88 Sheet.96 31 31 Sheet.98 Reserved Reserved Sheet.99 MultiPortDevCap MultiPortDevCap Sheet.100 ComnVersionCap ComnVersionCap Sheet.101 DevIDStat DevIDStat Sheet.1 X20744-070619 X20744-070619
Table 3. Primary Common Capabilities & Status I (DVSEC) Bit Definitions
Bits Name Reset Value Access Description
31:24 DevIDStat 0 R FW: Device ID Status
23:22 ComnVersionCap 0 R FW: Common Version Capability
21:3       Reserved
2:0 MultiportDevCap 0 R MultiPort Device Capability

Primary Common Capabilities & Status II (DVSEC) Register

Figure 2. Primary Common Capabilities & Status II (DVSEC) Register System Cache Page-1 Sheet.118 Sheet.92 Sheet.83 Sheet.56 Sheet.20 Sheet.2 Sheet.3 0 0 Sheet.4 Sheet.5 Sheet.6 1 1 Sheet.7 Sheet.8 Sheet.9 2 2 Sheet.10 Sheet.11 Sheet.12 3 3 Sheet.13 Sheet.15 4 4 Sheet.19 Sheet.21 6 6 Sheet.23 Sheet.24 7 7 Sheet.25 Sheet.26 Sheet.27 8 8 Sheet.28 Sheet.29 Sheet.30 9 9 Sheet.31 Sheet.33 10 10 Sheet.46 Sheet.57 18 18 Sheet.60 19 19 Sheet.73 Sheet.84 27 27 Sheet.87 28 28 Sheet.91 Sheet.93 30 30 Sheet.95 Sheet.96 31 31 Sheet.97 Sheet.98 Reserved Reserved Sheet.100 DevRdyTimeScale DevRdyTimeScale Sheet.101 DevRdyTimeValue DevRdyTimeValue Sheet.102 SAMAlignCap SAMAlignCap Sheet.103 PortAggCap PortAggCap Sheet.104 SoftwareServicePortalCap SoftwareServicePortalCap Sheet.105 AddrWidthCap AddrWidthCap Sheet.106 CacheLineSizeCap CacheLineSizeCap Sheet.107 MultiHopPortAggCap MultiHopPortAggCap Sheet.108 PartialCacheStatCap PartialCacheStatCap Sheet.109 DevDiscRdyStat DevDiscRdyStat Sheet.111 13 13 Sheet.112 Sheet.113 14 14 Sheet.114 Sheet.115 Sheet.116 15 15 Sheet.121 16 16 Sheet.122 Sheet.123 Reserved Reserved Sheet.124 DeviceQACK DeviceQACK Sheet.125 DeviceHWQACKCap DeviceHWQACKCap Sheet.126 Sheet.127 Reserved Reserved Sheet.1 X20745-070619 X20745-070619
Table 4. Primary Common Capabilities & Status II (DVSEC) Bit Definitions
Bits Name Reset Value Access Description
31       Reserved
30:28 DevRdyTimeScale 0 R FW: Readiness Time Scale
27:19 DevRdyTimeValue 0 R FW: Readiness Time Value
18:16       Reserved
15 DeviceHWQACKCap 0 R CCIX Device HW QACK Capability
14 DeviceQACK 0 R CCIX Device HW QACK
13:10       Reserved
9 SAMAlignCap 0 R SAM Alignment Capability
8 SoftwareServicePortalCap 0 R FW: CCIX Software Service Portal Capability
7 MultiHopPortAggrCap 0 R Multi-Hop Port Aggregation Capability
6:4 AddrWidthCap 0 R Address Width Capability
3 CacheLineSizeCap 0 R Cache Line Size Capability
2 PortAggCap 0 R Port Aggregation Capability
1 PartialCacheStatesCap 0 R Partial Cache State Capability
0 DevDiscRdyStat 1 R Device Discovery Register Status

Primary Common Capabilities & Status III (DVSEC) Register

Figure 3. Primary Common Capabilities & Status III (DVSEC) Register System Cache Page-1 Sheet.95 Sheet.3 0 0 Sheet.96 63 63 Sheet.97 Sheet.98 Reserved Reserved Sheet.1 X22826-070619 X22826-070619
Table 5. Primary Common Capabilities & Status III (DVSEC) Bit Definitions
Bits Name Reset Value Access Description
63:0       Reserved

Primary Common Control I (DVSEC) Register

Figure 4. Primary Common Control I (DVSEC) Register System Cache Page-1 Sheet.192 Sheet.168 Sheet.162 Sheet.144 Sheet.99 Sheet.100 0 0 Sheet.101 Sheet.102 Sheet.103 1 1 Sheet.104 Sheet.105 Sheet.106 2 2 Sheet.107 Sheet.108 Sheet.109 3 3 Sheet.110 Sheet.111 Sheet.112 4 4 Sheet.113 Sheet.114 Sheet.115 5 5 Sheet.116 Sheet.117 Sheet.118 6 6 Sheet.119 Sheet.120 Sheet.121 7 7 Sheet.122 Sheet.123 Sheet.124 8 8 Sheet.125 Sheet.127 9 9 Sheet.137 Sheet.145 15 15 Sheet.148 16 16 Sheet.158 Sheet.163 21 21 Sheet.166 22 22 Sheet.167 Sheet.169 23 23 Sheet.172 24 24 Sheet.182 Sheet.193 31 31 Sheet.195 Reserved Reserved Sheet.196 Reserved Reserved Sheet.197 DevIDCntl DevIDCntl Sheet.198 ErrAgentID ErrAgentID Sheet.199 SoftwareServicesPortEnable SoftwareServicesPortEnable Sheet.200 HSAMTblVal HSAMTblVal Sheet.201 RSAMTblVal RSAMTblVal Sheet.202 IDMTblVal IDMTblVal Sheet.203 PortAggEnable PortAggEnable Sheet.204 Reserved Reserved Sheet.205 MeshTopologyEnable MeshTopologyEnable Sheet.206 PrimaryPortEnable PrimaryPortEnable Sheet.207 DevEnable DevEnable Sheet.1 X20746-070619 X20746-070619
Table 6. Primary Common Control I (DVSEC) Bit Definitions
Bits Name Reset Value Access Description
31:24 DevIDCntl 0 R/W FW: DIDC
23:22       Reserved
21:16 ErrAgentID 0 R/W Error Agent ID
15:9       Reserved
8 SoftwareServicesPortEnable 0 R/W FW: Software Service Portal Enable
7 HSAMTblVal 0 R/W HSAM Table Valid
6 RSAMTblVal 0 R/W RSAM Table Valid
5 IDMTblVal 0 R/W FW: IDM Table Valid
4 PortAggEnable 0 R/W Port Aggregation Enable
3       Reserved
2 MeshTopologyEnable 0 R/W Mesh Topology Enable
1 PrimaryPortEnable 0 R/W Primary Port Enable
0 DevEnable 0 R/W Device Enable

Primary Common Control II (DVSEC) Register

Figure 5. Primary Common Control II (DVSEC) Register System Cache Page-1 Sheet.139 Sheet.95 Sheet.20 Sheet.2 Sheet.3 0 0 Sheet.4 Sheet.5 Sheet.6 1 1 Sheet.7 Sheet.8 Sheet.9 2 2 Sheet.10 Sheet.11 Sheet.12 3 3 Sheet.13 Sheet.15 4 4 Sheet.19 Sheet.21 6 6 Sheet.24 7 7 Sheet.96 31 31 Sheet.97 Sheet.98 Reserved Reserved Sheet.99 Reserved Reserved Sheet.124 Reserved Reserved Sheet.125 AddrWidthEnable AddrWidthEnable Sheet.126 CacheLineSizeEnable CacheLineSizeEnable Sheet.127 PartialCacheStatesEnable PartialCacheStatesEnable Sheet.128 13 13 Sheet.129 Sheet.130 Sheet.131 14 14 Sheet.132 Sheet.133 Sheet.134 15 15 Sheet.135 19 19 Sheet.136 Sheet.137 20 20 Sheet.138 Sheet.140 21 21 Sheet.141 Sheet.143 Reserved Reserved Sheet.144 QUACKTimeValue QUACKTimeValue Sheet.145 QUACKTimeScale QUACKTimeScale Sheet.146 DeviceQREQ DeviceQREQ Sheet.1 X20747-070619 X20747-070619
Table 7. Primary Common Control II (DVSEC) Bit Definitions
Bits Name Reset Value Access Description
31:21 QUACKTIMEValue 0 R/W QUACK Time Value
20 QUACKTimeScale 0 R/W QUACK Time Scale
19:15       Reserved
14 DeviceQREQ 0 R/W CCIX Device QREQ
13:7       Reserved
6:4 AddrWidthEnable 0 R/W Address Width Enable
3 CacheLineSizeEnable 0 R/W Cacheline Size Enable
2       Reserved
1 PartialCacheStatesEnable 0 R/W Partial Cache State Enable
0       Reserved

CCIX Device Error Control & Status Register

Figure 6. CCIX Device Error Control & Status Register System Cache Page-1 Sheet.2 Sheet.5 Sheet.6 0 0 Sheet.7 Sheet.10 Sheet.18 1 1 Sheet.20 31 31 Sheet.23 En En Sheet.24 Reserved Reserved Sheet.1 X22827-070619 X22827-070619
Table 8. CCIX Device Error Control & Status Bit Definitions
Bits Name Reset Value Access Description
31:1       Reserved
0 EN 0 R/W Error Reporting Enable

Primary PCIe & CCIX Common Register

Figure 7. Primary PCI & CCIX Common Register System Cache Page-1 Sheet.95 Sheet.80 Sheet.71 Sheet.47 Sheet.3 0 0 Sheet.25 Sheet.48 15 15 Sheet.51 16 16 Sheet.64 Sheet.72 23 23 Sheet.75 24 24 Sheet.79 Sheet.81 26 26 Sheet.83 Sheet.84 27 27 Sheet.85 Sheet.87 28 28 Sheet.94 Sheet.96 31 31 Sheet.98 Reserved Reserved Sheet.99 MSDA MSDA Sheet.100 TC TC Sheet.101 Tag Tag Sheet.102 VendorID VendorID Sheet.1 X20748-070619 X20748-070619
Table 9. Primary PCI & CCIX Common Bit Definitions
Bits Name Reset Value Access Description
31:28       Reserved
27 MSDA 0 R/W Move to SD Allowed
26:24 TC 0 R/W TC
23:16 Tag 0 R/W Tag
15:0 VendorID 0 R/W Vendor ID

Port Capability & Status I Register

Figure 8. Port Capability & Status I Register System Cache Page-1 Sheet.107 Sheet.108 Sheet.109 Sheet.95 Sheet.80 Sheet.56 Sheet.38 Sheet.2 Sheet.3 0 0 Sheet.4 Sheet.5 Sheet.6 1 1 Sheet.7 Sheet.9 2 2 Sheet.13 Sheet.15 4 4 Sheet.17 Sheet.18 5 5 Sheet.19 Sheet.20 Sheet.21 6 6 Sheet.22 Sheet.24 7 7 Sheet.31 Sheet.39 12 12 Sheet.42 13 13 Sheet.52 Sheet.57 18 18 Sheet.60 19 19 Sheet.73 Sheet.81 26 26 Sheet.84 27 27 Sheet.91 Sheet.96 31 31 Sheet.98 Reserved Reserved Sheet.99 PortID PortID Sheet.100 NumPSAMEntryCap NumPSAMEntryCap Sheet.101 NumLinksCap NumLinksCap Sheet.102 Reserved Reserved Sheet.103 PortToPortFwdingCap PortToPortFwdingCap Sheet.104 PktHdrTypeCap PktHdrTypeCap Sheet.105 Reserved Reserved Sheet.106 PortHWQACKCap PortHWQACKCap Sheet.110 3 3 Sheet.111 Sheet.112 PortQACK PortQACK Sheet.113 Sheet.114 PortDiscRdyStat PortDiscRdyStat Sheet.1 X20749-070619 X20749-070619
Table 10. Port Capability & Status I Bit Definitions
Bits Name Reset Value Access Description
31:27 PortÍD 0 R CCIX Port ID
26:19       Reserved
18:13 NumPSAMEntryCap 0x2 R FW: Number of PSAM Entries Capabilities
12:7 NumLinksCap 0x1 R Number of Links Capability
6       Reserved
5 PortToPortFwdingCap 0 R Port-to-Port Forward Capability
4 PortHWQACKCap 0 R Port HW QACK Capability
3 PortQAck 0 R Port QUACK
2       Reserved
1 PktHdrTypeCap 0 R Package Header Type Capability (Optimized)
0 PortDiscRdyStat 1 R CCIX Port Discover Status

Port Capability & Status II Register

Figure 9. Port Capability & Status II Register System Cache Page-1 Sheet.95 Sheet.47 Sheet.3 0 0 Sheet.31 Sheet.48 15 15 Sheet.51 16 16 Sheet.73 Sheet.96 31 31 Sheet.98 PortAggVctr(15:0) PortAggVctr(15:0) Sheet.99 Reserved Reserved Sheet.1 X20750-070619 X20750-070619
Table 11. Port Capability & Status II Bit Definitions
Bits Name Reset Value Access Description
31:16       Reserved
15:0 PortAggVctr 0 R FW: Aggregation with PortID15-PortID0

Port Capability & Status III Register

Figure 10. Port Capability & Status III Register System Cache Page-1 Sheet.31 Sheet.32 Sheet.33 0 0 Sheet.34 Sheet.35 15 15 Sheet.36 16 16 Sheet.37 Sheet.38 31 31 Sheet.39 PortFwdingVctr(15:0) PortFwdingVctr(15:0) Sheet.40 Reserved Reserved Sheet.1 X20751-070619 X20751-070619
Table 12. Port Capability & Status III Bit Definitions
Bits Name Reset Value Access Description
31:16       Reserved
15:0 PortFwdingvVctr 0 R FW: Forwarding to PortID15-PortID0

Port Error Control & Status 0 Register

Figure 11. Port Error Control & Status 0 Register System Cache Page-1 Sheet.130 Sheet.131 0 0 Sheet.134 1 1 Sheet.135 Sheet.136 Sheet.137 2 2 Sheet.140 3 3 Sheet.141 Sheet.142 Sheet.143 4 4 Sheet.186 Sheet.224 31 31 Sheet.226 Reserved Reserved Sheet.227 Dis Dis Sheet.228 Sta Sta Sheet.1 X20760-032420 X20760-032420
Table 13. Port Error Control & Status 0 Bit Definitions
Bits Name Reset Value Access Description
31:4       Reserved
3:2 Dis 0 R/W PER Disable
1:0 Sta 0 R/W Error Status

Port Error Control & Status 1 Register

Figure 12. Port Error Control & Status 1 Register System Cache Page-1 Sheet.3 Sheet.4 Sheet.5 Sheet.6 0 0 Sheet.7 Sheet.8 5 5 Sheet.9 6 6 Sheet.10 7 7 Sheet.11 Sheet.12 8 8 Sheet.13 Sheet.14 13 13 Sheet.15 Sheet.16 14 14 Sheet.17 Sheet.18 15 15 Sheet.19 Sheet.20 16 16 Sheet.21 Sheet.22 25 25 Sheet.23 Sheet.24 26 26 Sheet.25 Sheet.26 31 31 Sheet.27 Reserved Reserved Sheet.28 PerTypeMask PerTypeMask Sheet.29 Reserved Reserved Sheet.30 SevReportMask SevReportMask Sheet.31 Reserved Reserved Sheet.32 SevLogMask SevLogMask Sheet.1 X20761-032420 X20761-032420
Table 14. Port Error Control & Status 1 Bit Definitions
Bits Name Reset Value Access Description
31:26       Reserved
25:16 PerTypeMask 0 R/W PER Type Mask
15:14       Reserved
13:8 SevReportMask 0 R/W Severity Reporting Mask
7:6       Reserved
5:0 SevLogMask 0 R/W Severity Logging Mask

Port Control I Register

Figure 13. Port Control I Register System Cache Page-1 Sheet.104 Sheet.95 Sheet.56 Sheet.38 Sheet.20 Sheet.2 Sheet.3 0 0 Sheet.4 Sheet.5 Sheet.6 1 1 Sheet.7 Sheet.9 2 2 Sheet.16 Sheet.21 6 6 Sheet.24 7 7 Sheet.31 Sheet.39 12 12 Sheet.42 13 13 Sheet.49 Sheet.57 18 18 Sheet.60 19 19 Sheet.79 Sheet.96 31 31 Sheet.98 Reserved Reserved Sheet.99 Reserved Reserved Sheet.100 NumPSAMEntryEnable NumPSAMEntryEnable Sheet.101 NumlinksEnable NumlinksEnable Sheet.102 PortEnable PortEnable Sheet.103 PortQREQ PortQREQ Sheet.105 Sheet.106 3 3 Sheet.107 4 4 Sheet.108 Reserved Reserved Sheet.109 Sheet.110 Sheet.111 PktHdrTypeEnable PktHdrTypeEnable Sheet.1 X20752-070619 X20752-070619
Table 15. Port Control I Bit Definitions
Bits Name Reset Value Access Description
31:19       Reserved
18:13 NumPSMAEntryEnable 0 R/W FW: Number of PSAM Entries Enable
12:7 NumLinksEnable 0 R/W Number of Links Enable
6:4       Reserved
3 PortQREQ 0 R/W Port QREQ
2       Reserved
1 PktHdrTypeEnable 0 R/W Optimized Packet Header Type Enable
0 PortEnable 0 R/W Port Enable

Port Source Transport ID Map Register

Figure 14. Port Source Transport ID Map Register System Cache Page-1 Sheet.95 Sheet.47 Sheet.3 0 0 Sheet.25 Sheet.48 15 15 Sheet.51 16 16 Sheet.73 Sheet.96 31 31 Sheet.98 Reserved Reserved Sheet.99 RequestorID RequestorID Sheet.1 X20753-070619 X20753-070619
Table 16. Port Source Transport ID Map Bit Definitions
Bits Name Reset Value Access Description
31:16       Reserved
15:0 RequestorID 0 R/W Requestor ID

Port Link Tx Status Register

Figure 15. Port Link Tx Status Register System Cache Page-1 Sheet.2 Sheet.3 0 0 Sheet.4 Sheet.5 9 9 Sheet.6 Sheet.7 10 10 Sheet.8 Sheet.9 19 19 Sheet.10 Sheet.11 20 20 Sheet.12 Sheet.13 Sheet.14 29 29 Sheet.15 30 30 Sheet.16 Sheet.17 31 31 Sheet.18 Sheet.19 32 32 Sheet.20 Sheet.21 41 41 Sheet.22 Sheet.23 42 42 Sheet.24 Sheet.25 51 51 Sheet.26 Sheet.27 52 52 Sheet.28 Sheet.29 63 63 Sheet.30 Reserved Reserved Sheet.31 TxTLCL TxTLCL Sheet.32 TxMISCCL TxMISCCL Sheet.33 TxDATCL TxDATCL Sheet.34 TxSNPCL TxSNPCL Sheet.35 TxMEMCL TxMEMCL Sheet.36 Reserved Reserved Sheet.1 X20754-062220 X20754-062220
Table 17. Port Link Tx Status Bit Definitions
Bits Name Reset Value Access Description
63:52       Reserved
51:42 TxTLCL 0 R

CCIX: CXS Transaction Layer Credit Level available for use /

CHI: Reserved
41:32 TxMISCCL 0 R

CCIX: Misc Credit Level available for use /

CHI: TX Rsp Credit Level available for use
31:30       Reserved
29:20 TxDATCL 0 R

CCIX: Data Credit Level available for use /

CHI: TX Data Credit Level available for use

19:10 TxSNPCL 0 R

CCIX: Snoop Credit Level available for use /

CHI: RX Snoop Credit Level available for use
9:0 TxMEMCL 0 R

CCIX: Memory Request Credit Level available for use /

CHI: TX Req Credit Level available for use

Port Link Rx Status Register

Figure 16. Port Link Rx Status Register
Table 18. Port Link Rx Status Bit Definitions
Bits Name Reset Value Access Description
63 RxTLActReq 0 R

CCIX: CXS0_ACTIVE_REQ_RX value /

CHI: M0_CHI_RXLINKACTIVEREQ value
62 TxTLActAck 0 R

CCIX: CXS0_ACTIVE_ACK_TX value /

CHI: M0_CHI_TXLINKACTIVEACK value
61 TxTLDeActHint 0 R

CCIX: CXS0_DEACT_HINT_TX value /

CHI: RXLINK goes to Deactivate state
60 ChiSysCoAck 0 R

CCIX: Reserved /

CHI: M0_CHI_SYSCOACK value
59 ChiTxSActive 0 R

CCIX: Reserved /

CHI: M0_CHI_TXSACTIVE value
58 ChiRxSActive 0 R

CCIX: Reserved /

CHI: M0_CHI_RXSACTIVE value
57:52       Reserved
51:42 RxTLCL 0xF R

CCIX: CXS Transaction Layer Credit Level that can be granted /

CHI: Reserved
41:32 RxMISCCL 0 R

CCIX: Misc Credit Level that can be granted /

CHI: RX Rsp Credit Level that can be granted
31:30       Reserved
29:20 RxDATCL 0 R

CCIX Data Credit Level that can be granted /

CHI: RX Data Credit Level that can be granted
19:10 RxSNPCL 0 R

CCIX: Snoop Credit Level that can be granted /

CHI: RX Snoop Credit Level that can be granted
9:0 RxMEMCL 0 R

CCIX: Memory Request Credit Level that can be granted /

CHI: Reserved

Port Link BFCV0+BFCV1 Register

Figure 17. Port Link BFCV0+BFCV1 Register System Cache Page-1 Sheet.47 Sheet.95 Sheet.3 0 0 Sheet.25 Sheet.48 31 31 Sheet.51 32 32 Sheet.73 Sheet.96 63 63 Sheet.98 BCastFwdCntlVctr1 BCastFwdCntlVctr1 Sheet.99 BCastFwdCntlVctr0 BCastFwdCntlVctr0 Sheet.1 X20756-070619 X20756-070619
Table 19. Port Link BFCV0+BFCV1 Bit Definitions
Bits Name Reset Value Access Description
63:32 BCastFwdCntlVctr1 0 R/W FW: Broadcast Forward Control Vector1
31:0 BCastFwdCntlVctr0 0 R/W FW: Broadcast Forward Control Vector 0

Port Link Control I Register

Figure 18. Port Link Control I Register System Cache Page-1 Sheet.107 Sheet.95 Sheet.29 Sheet.17 Sheet.2 Sheet.3 0 0 Sheet.4 Sheet.5 Sheet.6 1 1 Sheet.7 Sheet.8 Sheet.9 2 2 Sheet.10 Sheet.12 3 3 Sheet.16 Sheet.18 5 5 Sheet.20 Sheet.21 6 6 Sheet.22 Sheet.24 7 7 Sheet.28 Sheet.30 9 9 Sheet.32 Sheet.33 10 10 Sheet.34 Sheet.36 11 11 Sheet.67 Sheet.96 31 31 Sheet.98 Reserved Reserved Sheet.99 LinkEntryAddrType LinkEntryAddrType Sheet.100 MaxPktSizeEnable MaxPktSizeEnable Sheet.101 NoCompAckEnable NoCompAckEnable Sheet.103 Reserved Reserved Sheet.104 LinkQREQ LinkQREQ Sheet.105 LinkCreditSendEnable LinkCreditSendEnable Sheet.106 LinkEnable LinkEnable Sheet.108 4 4 Sheet.109 Sheet.110 MsgPackingEnable MsgPackingEnable Sheet.1 X20755-070619 X20755-070619
Table 20. Port Link Control I Bit Definitions
Bits Name Reset Value Access Description
31:11       Reserved
10 LinkEntryAddrType 0 R/W FW: Link Entry Address Type
9:7 MaxPktSizeEnable 0 R/W Max Package Size Enable
6 NoCompAckEnable 0 R/W NoCompAck Enable
5:4       Reserved
3 LinkQREQ 0 R/W Link Quiescent Request
2 MsgPackingEnable 0 R/W Message Packing Entry
1 LinkCreditSendEnable 0 R/W CCIX Link Credit Send Enable
0 LinkEnable 0 R/W CCIX Link Enable

Port Link Control II Register

Figure 19. Port Link Control II Register System Cache Page-1 Sheet.95 Sheet.89 Sheet.59 Sheet.29 Sheet.3 0 0 Sheet.19 Sheet.30 9 9 Sheet.33 10 10 Sheet.46 Sheet.60 19 19 Sheet.63 20 20 Sheet.79 Sheet.90 29 29 Sheet.93 30 30 Sheet.96 31 31 Sheet.97 Sheet.98 Reserved Reserved Sheet.99 MaxDatReqCreditEnable MaxDatReqCreditEnable Sheet.100 MaxSnpReqCreditEnable MaxSnpReqCreditEnable Sheet.101 MaxMemReqCreditEnable MaxMemReqCreditEnable Sheet.1 X20757-070719 X20757-070719
Table 21. Port Link Control II Bit Definitions
Bits Name Reset Value Access Description
31:30       Reserved
29:20 MaxDatReqCreditEnable 0 R/W Maximum Data Request Credit Enable
19:10 MaxSnpReqCreditEnable 0 R/W Maximum Snoop Request Credit Enable
9:0 MaxMemReqCreditEnable 0 R/W Maximum Memory Request Credit Enable

Port Link Control III Register

Figure 20. Port Link Control III Register System Cache Page-1 Sheet.99 Sheet.100 Sheet.101 Sheet.102 Sheet.103 0 0 Sheet.104 Sheet.105 9 9 Sheet.106 10 10 Sheet.107 Sheet.108 19 19 Sheet.109 20 20 Sheet.110 Sheet.111 29 29 Sheet.112 30 30 Sheet.113 31 31 Sheet.114 Sheet.115 Reserved Reserved Sheet.119 Sheet.120 Sheet.121 Sheet.122 MinDatReqCreditEnable MinDatReqCreditEnable Sheet.123 MinSnpReqCreditEnable MinSnpReqCreditEnable Sheet.124 MinMemReqCreditEnable MinMemReqCreditEnable Sheet.1 X20758-070719 X20758-070719
Table 22. Port Link Control III Bit Definitions
Bits Name Reset Value Access Description
31:30       Reserved
29:20 MinDatReqCreditEnable 0 R/W Minimum Data Request Credit Enable
19:10 MinSnpReqCreditEnable 0 R/W Minimum Snoop Request Credit Enable
9:0 MinMemReqCreditEnable 0 R/W Minimum Memory Request Credit Enable

Port Link Control IV Register

Figure 21. Port Link Control IV Register System Cache Page-1 Sheet.1 Sheet.3 Sheet.4 Sheet.5 0 0 Sheet.6 Sheet.7 9 9 Sheet.8 10 10 Sheet.9 Sheet.10 19 19 Sheet.11 20 20 Sheet.15 31 31 Sheet.16 Sheet.17 Reserved Reserved Sheet.19 MinMiscReqCreditEnable MinMiscReqCreditEnable Sheet.20 MaxMiscReqCreditEnable MaxMiscReqCreditEnable Sheet.21 X20759-070719 X20759-070719
Table 23. Port Link Control IV Bit Definitions
Bits Name Reset Value Access Description
31:20       Reserved
19:10 MinMiscReqCreditEnable 0 R/W Minimum Request Credit Enable
9:0 MaxMiscReqCreditEnable 0 R/W Maximum Misc Request Credit Enable

Port Link Error Control & Status 0 Register

Figure 22. Port Link Error Control & Status 0 Register System Cache Page-1 Sheet.130 Sheet.131 0 0 Sheet.134 1 1 Sheet.135 Sheet.136 Sheet.137 2 2 Sheet.140 3 3 Sheet.141 Sheet.142 Sheet.143 4 4 Sheet.186 Sheet.224 31 31 Sheet.226 Reserved Reserved Sheet.227 Dis Dis Sheet.228 Sta Sta Sheet.1 X20760-032420 X20760-032420
Table 24. Port Link Error Control & Status 0 Bit Definitions
Bits Name Reset Value Access Description
31:4       Reserved
3:2 Dis 0 R/W PER Disable
1:0 Sta 0 R/W Error Status

Port Link Error Control & Status 1 Register

Figure 23. Port Link Error Control & Status 1 Register System Cache Page-1 Sheet.3 Sheet.4 Sheet.5 Sheet.6 0 0 Sheet.7 Sheet.8 5 5 Sheet.9 6 6 Sheet.10 7 7 Sheet.11 Sheet.12 8 8 Sheet.13 Sheet.14 13 13 Sheet.15 Sheet.16 14 14 Sheet.17 Sheet.18 15 15 Sheet.19 Sheet.20 16 16 Sheet.21 Sheet.22 25 25 Sheet.23 Sheet.24 26 26 Sheet.25 Sheet.26 31 31 Sheet.27 Reserved Reserved Sheet.28 PerTypeMask PerTypeMask Sheet.29 Reserved Reserved Sheet.30 SevReportMask SevReportMask Sheet.31 Reserved Reserved Sheet.32 SevLogMask SevLogMask Sheet.1 X20761-032420 X20761-032420
Table 25. Port Link Error Control & Status 1 Bit Definitions
Bits Name Reset Value Access Description
31:26       Reserved
25:16 PerTypeMask 0 R/W PER Type Mask
15:14       Reserved
13:8 SevReportMask 0 R/W Severity Reporting Mask
7:6       Reserved
5:0 SevLogMask 0 R/W Severity Logging Mask

Port Link Destination TransportID Map Register

Figure 24. Port Link Destination TransportID Map Register System Cache Page-1 Sheet.95 Sheet.3 0 0 Sheet.28 Sheet.47 Sheet.48 15 15 Sheet.51 16 16 Sheet.73 Sheet.96 31 31 Sheet.98 Reserved Reserved Sheet.99 DestTransportID DestTransportID Sheet.1 X20762-070719 X20762-070719
Table 26. Port Link Destination TransportID Map Bit Definitions
Bits Name Reset Value Access Description
31:16       Reserved
15:0 DestTransportID 0 R/W Destination Transport ID

SC Specific Port Link Specific Register

Figure 25. SC Specific Port Link Specific Register System Cache Page-1 Sheet.403 Sheet.402 Sheet.386 Sheet.320 Sheet.308 Sheet.294 0 0 Sheet.301 Sheet.309 5 5 Sheet.312 6 6 Sheet.316 Sheet.321 9 9 Sheet.323 Sheet.324 10 10 Sheet.325 Sheet.326 Sheet.327 11 11 Sheet.328 Sheet.329 Sheet.330 12 12 Sheet.331 Sheet.332 Sheet.333 13 13 Sheet.334 Sheet.335 Sheet.336 14 14 Sheet.337 Sheet.338 Sheet.339 15 15 Sheet.340 Sheet.341 Sheet.342 16 16 Sheet.343 Sheet.344 Sheet.345 17 17 Sheet.346 Sheet.347 Sheet.348 18 18 Sheet.349 Sheet.350 Sheet.351 19 19 Sheet.352 Sheet.354 20 20 Sheet.370 Sheet.387 31 31 Sheet.389 Reserved Reserved Sheet.390 NRRA NRRA Sheet.391 ENCOHCHI ENCOHCHI Sheet.392 SINRRA SINRRA Sheet.393 PLRSTC PLRSTC Sheet.394 PLRETC PLRETC Sheet.395 PLEXCC PLEXCC Sheet.396 TLRSTC TLRSTC Sheet.397 TLRETC TLRETC Sheet.398 TLEXCC TLEXCC Sheet.399 TLACTC TLACTC Sheet.400 MCL MCL Sheet.401 TGTID TGTID Sheet.404 21 21 Sheet.405 22 22 Sheet.406 Sheet.407 TLDEHI TLDEHI Sheet.408 Sheet.409 FTXLACT FTXLACT Sheet.1 X20763-070719 X20763-070719
Table 27. SC Specific Port Link Specific Bit Definitions
Bits Name Reset Value Access Description
31:22       Reserved
21 FTXLACT 0 R/W Reserved (Force TX Link activation)
20 TLDEHI 0 R/W

CCIX: Transaction Layer Deactivation Hint /

CHI: Reserved
19 NRRA 0 R/W Reserved (No Remote RA)
18 ENCOHCHI 0 R/W

CCIX: Reserved /

CHI: Enable coherency by using the System Coherency handshake
17 SNRRA 0 R/W Reserved (Single Remote RA)
16 PLRSTC 0 R/W

CCIX: Protocol Layer Reset Credits /

CHI: Reserved
15 PLRETC 0 R/W

CCIX: Protocol Layer Return Credits /

CHI: Reserved
14 PLEXCC 0 R/W

CCIX: Protocol Layer Exchange Credits /

CHI: Reserved
13 TLRSTC 0 R/W Transaction Layer Reset Credits
12 TLRETC 0 R/W Transaction Layer Return Credits
11 TLEXCC 0 R/W Transaction Layer Exchange Credits
10 TLACTC 0 R/W Transaction Layer Activate Connection
9:6 MCL 0 R/W Reserved (Max Chain Length)
5:0 TGTID 0 R/W

CCIX: TgtID, when Sending Credit Exchange /

CHI: Reserved

Port Link Capability & Status I Register

Figure 26. Port Link Capability & Status I Register System Cache Page-1 Sheet.95 Sheet.29 Sheet.17 Sheet.2 Sheet.3 0 0 Sheet.4 Sheet.5 Sheet.6 1 1 Sheet.7 Sheet.8 Sheet.9 2 2 Sheet.10 Sheet.16 Sheet.18 5 5 Sheet.20 Sheet.21 6 6 Sheet.22 Sheet.24 7 7 Sheet.28 Sheet.30 9 9 Sheet.33 10 10 Sheet.64 Sheet.96 31 31 Sheet.98 Reserved Reserved Sheet.99 Reserved Reserved Sheet.100 MaxPktSizeCap MaxPktSizeCap Sheet.101 NonCompAckCap NonCompAckCap Sheet.102 MsgPackingCap MsgPackingCap Sheet.103 LinkDiscRdyStat LinkDiscRdyStat Sheet.104 LinkCreditType LinkCreditType Sheet.105 Sheet.106 Sheet.12 3 3 Sheet.107 4 4 Sheet.108 Sheet.109 Sheet.110 LinkHWQACKCap LinkHWQACKCap Sheet.111 LinkQACK LinkQACK Sheet.1 X20764-062220 X20764-062220
Table 28. Port Link Capability & Status I Bit Definitions
Bits Name Reset Value Access Description
31:10       Reserved
9:7 MaxPktSizeCap 0 R Max Package Size Capability
6 NoCompAckCap 0 R NoCompAck Capability
5       Reserved
4 LinkHWQACKCap 0 R Link’s Hardware Quiesce Acknowledgment Capability
3 LinkQACK 0 R Link’s Quiesce Acknowledgment status
2 MsgPackingCap 0 R Message Packing Capability
1 LinkCreditType 0 R CCIX Link Credit Type
0 LinkDiscRdyStat 1 R CCIX Link Discovery Status

Port Link Capability & Status II Register

Figure 27. Port Link Capability & Status II Register System Cache Page-1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 0 0 Sheet.7 Sheet.8 9 9 Sheet.9 10 10 Sheet.10 Sheet.11 19 19 Sheet.12 20 20 Sheet.13 Sheet.14 29 29 Sheet.15 30 30 Sheet.16 31 31 Sheet.17 Sheet.18 MaxDatReqSendCap MaxDatReqSendCap Sheet.19 MaxSnpReqSendCap MaxSnpReqSendCap Sheet.20 MaxMemReqSendCap MaxMemReqSendCap Sheet.21 Reserved Reserved Sheet.1 X20765-092419 X20765-092419
Table 29. Port Link Capability & Status II Bit Definitions
Bits Name Reset Value Access Description
31:30       Reserved
29:20 MaxDatReqSendCap N 1 R Maximum Data Request Send Capability
19:10 MaxSnpReqSendCap M 2 R Maximum Snoop Request Send Capability
9:0 MaxMemReqSendCap N 1 R Maximum Memory Request Send Capability
  1. N = C_NUM_SLAVE_TRANSACTIONS * (C_NUM_OPTIMIZED_PORTS + C_NUM_GENERIC_PORTS)
  2. M = C_NUM_SNOOP_TRANSACTIONS

Port Link Capability & Status III Register

Figure 28. Port Link Capability & Status III Register System Cache Page-1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 0 0 Sheet.7 Sheet.8 9 9 Sheet.9 10 10 Sheet.10 Sheet.11 19 19 Sheet.12 20 20 Sheet.13 Sheet.14 29 29 Sheet.15 30 30 Sheet.16 31 31 Sheet.17 Sheet.18 MaxDatReqRcvCap MaxDatReqRcvCap Sheet.19 MaxSnpReqRcvCap MaxSnpReqRcvCap Sheet.20 MaxMemReqRcvCap MaxMemReqRcvCap Sheet.21 Reserved Reserved Sheet.1 X20766-092419 X20766-092419
Table 30. Port Link Capability & Status III Bit Definitions
Bits Name Reset Value Access Description
31:30       Reserved
29:20 MaxDatReqRcvCap N 1 R Maximum Data Request Receive Capability
19:10 MaxSnpReqRcvCap M 2 R Maximum Snoop Request Receive Capability
9:0 MaxMemReqRcvCap N 1 R Maximum Memory Request Receive Capability
  1. N = C_NUM_MASTER_TRANSACTIONS / C_NUM_LINKS
  2. M = C_NUM_SNOOP_TRANSACTIONS / C_NUM_LINKS

Port Link Capability & Status IV Register

Figure 29. Port Link Capability & Status IV Register System Cache Page-1 Sheet.2 Sheet.3 Sheet.4 Sheet.5 0 0 Sheet.6 Sheet.7 9 9 Sheet.8 10 10 Sheet.9 Sheet.10 19 19 Sheet.11 20 20 Sheet.12 31 31 Sheet.13 Sheet.14 Reserved Reserved Sheet.15 MaxMiscReqRcvCap MaxMiscReqRcvCap Sheet.16 MaxMiscReqSendCap MaxMiscReqSendCap Sheet.1 X20767-070719 X20767-070719
Table 31. Port Link Capability & Status IV Bit Definitions
Bits Name Reset Value Access Description
31:20       Reserved
19:10 MaxMiscReqRcvCap 0x10 R Maximum Misc Request Send Capability
9:0 MaxMiscReqSendCap 0x10 R Maximum Misc Request Receive Capability

RA Capability & Status I Register

Figure 30. RA Capability & Status I Register System Cache Page-1 Sheet.112 Sheet.103 Sheet.2 Sheet.3 0 0 Sheet.4 Sheet.5 Sheet.6 1 1 Sheet.28 Sheet.57 18 18 Sheet.59 Sheet.60 19 19 Sheet.73 Sheet.84 27 27 Sheet.86 Sheet.87 28 28 Sheet.91 Sheet.93 30 30 Sheet.95 Sheet.96 31 31 Sheet.97 Sheet.98 Reserved Reserved Sheet.99 CacheFlushTimeValue CacheFlushTimeValue Sheet.100 CachFlushTimeScale CachFlushTimeScale Sheet.101 RACacheFlushStat RACacheFlushStat Sheet.102 RADiscRdyStat RADiscRdyStat Sheet.105 Sheet.106 Sheet.107 2 2 Sheet.108 3 3 Sheet.109 4 4 Sheet.110 5 5 Sheet.111 17 17 Sheet.113 Sheet.114 RAQUACK RAQUACK Sheet.115 Reserved Reserved Sheet.116 Sheet.117 Sheet.118 RAHWQUACKCap RAHWQUACKCap Sheet.119 Sheet.120 RAPreciseSnpRespCap RAPreciseSnpRespCap Sheet.1 X20775-072919 X20775-072919
Table 32. RA Capability & Status I Bit Definitions
Bits Name Reset Value Access Description
31 RACacherFlushStat 0 R Cache Flush Status
30:28 CacheFlushTimeScale 0 R Cache Flush Completion Time Scale
27:19 CacheFlushTimeValue 0 R Cache Flush Completion Time Value
18 RAPreciseSnpRespCap 0 R RA Precise Snp Resp Capability
17:5       Reserved
4 RAHWQUACKCap 0 R RA HW QUACK Capability
3 RAQUACK 0 R RA QACK
2:1       Reserved
0 RADiscRdyStat 1 R Request Agent Discovery Status

RA Control I Register

Figure 31. RA Control I Register System Cache Page-1 Sheet.108 Sheet.106 Sheet.95 Sheet.77 Sheet.2 Sheet.3 0 0 Sheet.4 Sheet.5 Sheet.6 1 1 Sheet.7 Sheet.8 Sheet.9 2 2 Sheet.25 Sheet.42 13 13 Sheet.44 Sheet.45 14 14 Sheet.46 Sheet.49 Sheet.64 Sheet.78 25 25 Sheet.81 26 26 Sheet.88 Sheet.96 31 31 Sheet.98 Reserved Reserved Sheet.99 Reserved Reserved Sheet.100 RAID RAID Sheet.101 RACacheEnable RACacheEnable Sheet.102 RACacheFlushEnable RACacheFlushEnable Sheet.103 RASnpRspEnable RASnpRspEnable Sheet.104 RAEnable RAEnable Sheet.105 Sheet.107 3 3 Sheet.109 4 4 Sheet.110 Sheet.111 RAQREQ RAQREQ Sheet.112 Reserved Reserved Sheet.117 Sheet.119 18 18 Sheet.120 19 19 Sheet.121 Reserved Reserved Sheet.122 Sheet.123 Sheet.124 RAEvictHintCntl RAEvictHintCntl Sheet.125 Sheet.126 RAWriteEvictFullHintCntl RAWriteEvictFullHintCntl Sheet.115 Sheet.51 16 16 Sheet.116 Sheet.118 17 17 Sheet.47 Sheet.48 15 15 Sheet.1 X20777-072919 X20777-072919
Table 33. RA Control I Bit Definitions
Bits Name Reset Value Access Description
31:26 RAID 0 R/W Request Agent ID
25:19       Reserved
18 RAWriteEvictFullHintCntl 0 R/W RA WriteEvictFull Hint Control
17 RAEvictHintCntl 0 R/W RA Evict Hint Control
16       Reserved
15 RACacheFlushEnable 0 R/W Cache Flush Enable
14 RACacheEnable 0 R/W Cache Enable
13:4       Reserved
3 RAQREQ 0 R/W RA QREQ
2       Reserved
1 RASnpRspEnable 0 R/W RA Snoop Response Enable
0 RAEnable 0 R/W Request Agent Enable

RA Error Control Status 0 Register

Figure 32. RA Error Control Status 0 Register System Cache Page-1 Sheet.95 Sheet.11 Sheet.5 Sheet.3 0 0 Sheet.4 Sheet.6 1 1 Sheet.9 2 2 Sheet.12 3 3 Sheet.13 Sheet.15 4 4 Sheet.55 Sheet.96 31 31 Sheet.98 Reserved Reserved Sheet.99 DIS DIS Sheet.100 STA STA Sheet.1 X20772-070719 X20772-070719
Table 34. RA Error Control Status 0 Bit Definitions
Bits Name Reset Value Access Description
31:4       Reserved
3:2 DIS 0 R/W PER Disable (LogDis and Dis)
1:0 STA 0 R/W Error Status (Sta)

RA Error Control Status 1 Register

Figure 33. RA Error Control Status 1 Register System Cache Page-1 Sheet.41 Sheet.23 Sheet.17 Sheet.3 0 0 Sheet.10 Sheet.18 5 5 Sheet.21 6 6 Sheet.24 7 7 Sheet.25 Sheet.27 8 8 Sheet.34 Sheet.42 13 13 Sheet.44 Sheet.45 14 14 Sheet.46 Sheet.48 15 15 Sheet.50 Sheet.51 16 16 Sheet.64 Sheet.78 25 25 Sheet.80 Sheet.81 26 26 Sheet.91 Sheet.96 31 31 Sheet.98 Reserved Reserved Sheet.99 PerTypeMask PerTypeMask Sheet.100 Reserved Reserved Sheet.101 SevReportMask SevReportMask Sheet.102 Reserved Reserved Sheet.103 SevLogMask SevLogMask Sheet.1 X20773-070719 X20773-070719
Table 35. RA Error Control Status 1 Bit Definitions
Bits Name Reset Value Access Description
31:26       Reserved
25:16 PerTypeMask 0 R/W PER Type Mask
15:14       Reserved
13:8 SevReportMask 0 R/W Severity Reporting Mask
7:6       Reserved
5:0 SevLogMask 0 R/W Severity Logging Mask

RA System Cache Specific Register

Figure 34. RA System Cache Specific Register System Cache Page-1 Sheet.452 Sheet.98 Sheet.99 0 0 Sheet.112 Sheet.129 10 10 Sheet.131 Sheet.132 11 11 Sheet.139 Sheet.144 15 15 Sheet.146 Sheet.147 16 16 Sheet.148 Sheet.149 Sheet.150 17 17 Sheet.151 Sheet.152 Sheet.153 18 18 Sheet.154 Sheet.155 Sheet.156 19 19 Sheet.157 Sheet.158 Sheet.159 20 20 Sheet.160 Sheet.161 Sheet.162 21 21 Sheet.163 Sheet.164 Sheet.165 22 22 Sheet.166 Sheet.167 Sheet.168 23 23 Sheet.169 Sheet.170 Sheet.171 24 24 Sheet.172 Sheet.173 Sheet.174 25 25 Sheet.175 Sheet.176 Sheet.177 26 26 Sheet.184 Sheet.192 31 31 Sheet.194 Reserved Reserved Sheet.292 Sheet.293 32 32 Sheet.342 Sheet.386 63 63 Sheet.388 Reserved Reserved Sheet.389 RNFID RNFID Sheet.440 Reserved Reserved Sheet.441 SNPOKEEP SNPOKEEP Sheet.442 SNPCLNSHKEEP SNPCLNSHKEEP Sheet.443 SNPTOSCKEEP SNPTOSCKEEP Sheet.444 SNPOPASS SNPOPASS Sheet.445 SNPOKEEP SNPOKEEP Sheet.446 SNPNSDPASS SNPNSDPASS Sheet.447 SNPCLPASS SNPCLPASS Sheet.448 SNPNSDKEEP SNPNSDKEEP Sheet.449 SNPSHKEEP SNPSHKEEP Sheet.450 SNPSHPASS SNPSHPASS Sheet.453 35 35 Sheet.454 36 36 Sheet.455 Sheet.456 QoS QoS Sheet.1 X20778-070719 X20778-070719
Table 36. RA System Cache Specific Bit Definitions
Bits Name Reset Value Access Description
63:45       Reserved
44 SNPNSDFWDPASS 0 R/W SnpNSDFwd Pass Dirty
43 SNPNSDFWDKEEP 0 R/W SnpNSDFwd Keep Line
42 SNPSHFWDHOME 0 R/W SnpSharedFwd Dirty Home, move dirty data to Home instead of requesting RN
41 SNPSHFWDPASS 0 R/W SnpSharedFwd Pass Dirty
40 SNPSHFWDKEEP 0 R/W SnpSharedFwd Keep Line
39 SNPCLFWDPASS 0 R/W SnpCleanFwd Pass Dirty
38 SNPCLFWDKEEP 0 R/W SnpCleanFwd Keep Line
37 SNPOFWDPASS 0 R/W SnpOnceFwd Pass Dirty
36 SNPOFWDKEEP 1 R/W SnpOnceFwd Keep Line
35:32 QoS 0x10 R/W Quality of Service
31:26       Reserved
25 SNPCLNSHKEEP 0 R/W SnpCleanShared Keep Line
24 SNPTOSCKEEP 0 R/W SnpToSC Keep Line
23 SNPNSDPASS 0 R/W SnpNSD Pass Dirty
22 SNPNSDKEEP 0 R/W SnpNSD Keep Line
21 SNPSHPASS 0 R/W SnpShared Pass Dirty
20 SNPSHKEEP 0 R/W SnpShared Keep Line
19 SNPCLPASS 0 R/W SnpClean Pass Dirty
18 SNPCLKEEP 0 R/W SnpClean Keep Line
17 SNPOPASS 0 R/W SnpOnce Pass Dirty
16 SNPOKEEP 1 R/W SnpOnce Keep Line
15:11       Reserved
10:0 RNFID 0 R/W RN-F NodeID (CHI only)