The CCIX master interface is compliant to the CCIX Base Specification Revision 1.1 Version 1.0. The following features are supported:
- CXS interface 256 and 512 bits data width, and 1024 bits data width for Versal Premium devices
- Optimized and Compatible header
- Packing enabled or disabled
- Chaining of memory requests
- One CCIX Port
- One CCIX link per port
- One Request Agent (RA)
- 64 byte cache line
- All available sizes are supported for Read and Write requests
- All address widths (48, 52, 56, 60 and 64-bit)
- 128, 256 and 512 byte Maximum Packet Size (MPS)
- The following transactions are generated under normal conditions:
-
ReadNoSnp,ReadOnce,ReadUnique,ReadShared,CleanShared,CleanUnique,CleanInvalid,MakeInvalid,WriteNoSnp,WriteUnique,WriteBackFullSD,WriteBackFullUD
-
- The following transactions can be generated when Atomics is
enabled:
-
AtomicStore_ADD,AtomicStore_CLR,AtomicStore_EOR,AtomicStore_SET,AtomicStore_SMAX,AtomicStore_SMIN,AtomicStore_UMAX,AtomicStore_UMIN,AtomicLoad_ADD,AtomicLoad_CLR,Atomicoad_EOR,AtomicLoad_SET,AtomicLoad_SMAX,AtomicLoad_SMIN,AtomicLoad_UMAX,AtomicLoad_UMIN,AtomicSwap,AtomicCompare - SnpME variants of Atomics
-
- All snoop combinations