Memory Controller AXI4 Master Interface Parameters - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

Document ID
PG118
Release Date
2021-11-05
Version
5.0 English
Table 1. Memory Controller AXI4 Master Interface Parameters
Parameter Name Feature/Description Allowable Values Default Value VHDL Type
C_M0_AXI_ADDR_WIDTH Address Width. Constant value. 32 32 natural
C_M0_AXI_DATA_WIDTH Data Width

32, 64, 128,

256, 512

32 natural
C_M0_AXI_THREAD_ID_WIDTH

ID width. Automatically assigned

with manual override

1-32 1 natural
C_M0_AXI_RRESP_WIDTH

Width of RRESP.

Automatically assigned.

2, 4 2 natural