The cache memory provides the actual cache functionality in the core. The cache is configurable in terms of size and associativity.
The cache size can be configured with the parameter C_CACHE_SIZE according to User Parameters. The selected size is a
trade-off between performance and resource usage, in particular the number of on-chip
RAMs.
The associativity can be configured with the parameter C_NUM_WAYS according to User Parameters. Increased associativity generally
provides better hit rate, which gives better performance but requires more area
resources.
The type of memory used for Tags, Data and LRU can be configured with the
parameters C_CACHE_TAG_MEMORY_TYPE, C_CACHE_DATA_MEMORY_TYPE and C_CACHE_LRU_MEMORY_TYPE respectively. The possible values are Automatic, LUTRAM, BRAM and URAM, except that
LUTRAM cannot be selected for Data. Additionally,
it is only possible to select URAM for UltraScale+ devices. The default configuration, Automatic, is generally recommended, but for larger cache
sizes selecting URAM for Data (if possible) will
provide better resource utilization.
The correspondence between selected parameters and on-chip RAMs used can be found in Performance and Resource Utilization.