Simulation Debug - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

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5.0 English

The simulation debug flow for Mentor Graphics Questa Advanced Simulator is described below. A similar approach can be used with other simulators.

  • Check for the latest supported versions of Questa Advanced Simulator in the Xilinx® Design Tools: Release Notes Guide. Is this version being used? If not, update to this version.
  • If using Verilog, do you have a mixed mode simulation license? If not, obtain a mixed-mode license.
  • Ensure that the proper libraries are compiled and mapped. In the Vivado® Design Suite this is done within the tool using Flow > Simulation Settings.
  • Have you associated the intended software program for all connected MicroBlaze™ processors with the simulation? Use Tools > Associate ELF Files in the Vivado® Design Suite to do this.
  • When observing the traffic on any of the AXI4 interfaces connected to the System Cache core, see the AMBA® AXI and ACE Protocol Specification for the AXI4 timing.