CCIX Property Translation - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

Document ID
PG118
Release Date
2024-12-09
Version
5.0 English

Incoming transactions on slave ports, cache maintenance operation via the control port, as well as the current cache line state determine the kind of transactions output on the CCIX interface, if any at all. The following tables show all types of events. Note that some of the write related events actually appear on the read channel.

Table 1. Read Request and Memory Type for Cache Originating Transactions
Event Request Memory Request
Read Miss not Allocating ReadNoSnp Device-nRnE

Device-nRE

Non-Cached

0x00
Read Miss not Allocating (coherent) ReadOnce WBnA 0x01
Read Miss Allocating ReadShared WBA 0x07
Read Hit (any type) No bus event
Write Miss Allocating ReadUnique WBnA/WBA 0x04
Write Hit Shared CleanUnique WBnA/WBA 0x10
Table 2. Write Request and Memory Type for Cache Originating Transactions
Event Request Memory Request
Write Miss not Allocating WriteNoSnp Device-nRnE

Device-nRE

Non-Cached

0x20
Write Miss not Allocating (coherent) WriteUnique WBnA 0x22
Evicting Dirty Line 1 WriteBack WBA 0x27
Write Hit Unique No bus event
  1. Reusing line or flushing