AXI4-Stream Interfaces - 5.0 English

AXI4-Stream Slaves (CQ/RC):

The input ATS0_S_AXIS_xx_VALID is asserted when address, data/response, and user channel input ATS0_S_AXIS_xx_TUSER are valid.

Normally, the input ATS0_S_AXIS_xx_TLAST is asserted when the last data/response in a beat is valid, simultaneously with ATS0_S_AXIS_xx_VALID.

However, when the AXI4-Stream straddle option is enabled, the TLP to decode consist of start/end pointer(s) in the ATS0_S_AXIS_xx_TUSER user channel input, indicating when the last data in a beat is valid, and the input ATS0_S_AXIS_xx_TLAST is inactive.

The interface response output ATS0_S_AXIS_xx_READY is asserted when the data/response is accepted. If the System Cache is not ready, the master side should wait while keeping all inputs unchanged.

The user channel input ATS0_S_AXIS_xx_TUSER encodes information regarding framing, byte alignment, parity, and the start/end pointers mentioned above. Decoding depends on the data width and PASID mode, see Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343) for details.

AXI4-Stream Masters: (CC/RQ):

The output ATS0_M_AXIS_xx_VALID is asserted when address, data/response, and user channel output ATS0_M_AXIS_xx_TUSER are valid.

Normally, the output ATS0_M_AXIS_xx_TLAST is asserted when the last data/response in a beat is valid, simultaneously with ATS0_M_AXIS_xx_VALID.

However, when the AXI4-Stream straddle option is enabled, the TLP to encode consist of start/end pointer(s) in the ATS0_M_AXIS_xx_TUSER user channel output, indicating when the last data in a beat is valid, and the output ATS0_M_AXIS_xx_TLAST is inactive.

The interface response input ATS0_M_AXIS_xx_READY should be asserted when the data/response is accepted. If the slave side is not ready, System Cache waits while keeping all outputs unchanged.

The user channel output ATS0_M_AXIS_xx_TUSER encodes information regarding framing, byte alignment, parity, and the start/end pointers mentioned above. Encoding depends on the data width and PASID mode, see Versal ACAP Integrated Block for PCI Express LogiCORE IP Product Guide (PG343) for details.

If the interface is unresponsive, ensure that the following conditions are met:

• The ACLK input is connected and toggling.
• The interface is not being held in reset, and ARESETN is an active-Low reset.
• If the simulation has been run, verify in simulation and/or a Vivado® debugging tool capture that the waveform is correct for accessing the AXI4-Stream interface.