Cache Coherent Interconnect for Accelerators (CCIX®) cache coherency is used for multiple devices with system wide cache coherency. System Cache provides one Request Agent (RA) that can access multiple Home Agents (HA). It provides up to four AXI4 interfaces for accelerators to connect to as shown in the following figure.
System Cache connects to the PCIe® block with one CXS point-to-point interface in each direction and with four AXI4-Stream interfaces when ATS address translation is enabled. The FPGA is connected to other devices via PCIe, which will tunnel CCIX traffic on a Virtual Channel (VC). These devices must contain one or more HAs, and possibly even internal RAs, as well as connect to other devices with additional RAs and/or HAs.
System Cache connects to the PCIe with a CXS/CCIX point-to-point interface similar to CCIX XDMA, with replacement of the XDMA PCIe block by the CCIX enabled CPM PCIe connectivity extension and with four AXI4-Stream interfaces when ATS address translation is enabled. Furthermore, the PASID Host propagation is supported, if enabled by Host support. An ATS switch is included to distribute ATS traffic to the System Cache instance, with dual clock configuration to allow System Cache single clock usage, even with configurable asynchronous PCIe clock domain.