The System Cache core can be added to an AXI4 system to improve overall system computing performance, for accesses to external memory.
With cache coherency, efficient multi-processor systems can be implemented and the workload distributed between multiple processors or accelerators, with simple and safe data sharing. The coherency is managed on a hardware level with minimal software handling required.
The System Cache core can provide improved system performance for:
- Applications with repeated access of data occupying a certain address range, for example, when external memory is used to buffer data during computations. In particular, performance improvements are achieved when the data set exceeds the capacity of the MicroBlaze™ processor internal data cache.
- Systems with small MicroBlaze processor caches, for example, when the MicroBlaze processor implementation is tuned to achieve as high frequency as possible. In this case, the increased system frequency contributes to the performance improvements, and the System Cache core alleviates the performance loss incurred by the reduced size of the MicroBlaze processor internal caches.
- Accelerators working on data sets that are shared between multiple accelerators and the Application Processing Unit (APU) in the Zynq® UltraScale+™ MPSoC. The cache coherency ensures all participating units can share data safely and efficiently.
- Accelerators working on data sets that are shared between multiple accelerators and a remote PCIe® host using the Cache Coherent Interconnect for Accelerators (CCIX®) cache coherency protocol. The cache coherency ensures all participating units share data safely and efficiently. PCIe Address Translation Services, ATS, with optional Process Address Space ID (PASID) support (technology dependent option), is provided to give accelerators the possibility to use virtual memory synchronized with the host.
- Accelerators connecting to System Cache in Versal® using a CHI connection to the Versal CCIX PCIe Module (CPM) for local coherency. The coherency domain can be extended from the CPM to include other devices by utilizing CCIX. System wide address translation is performed by ATS with PASID support.. This solution provides support for both local and remote memory.