All transactions in the Master Coherent configuration always have ARDOMAIN and
AWDOMAIN set to InnerShareable, unless the parameter C_DEFAULT_DOMAIN is changed from its default value.
There are three possible sources for transactions on the Master ACE port:
- DVM inserted from the control interface as well as automatic DVM sync responses.
- Inserted Barriers from the control interface.
- Traffic related to cache events directly from transactions or indirectly as a flush from the control interface.
The following table show the transaction settings for DVM type operations.
| Transaction | M0_AXI_ARCACHE | M0_AXI_ARSNOOP |
|---|---|---|
| DVM Message or DVM Sync | 0010 | 1111 |
| DVM Complete 1 | 0010 | 1110 |
|
||
The following tables show the transactions settings for Barrier type operations on read and write channels respectively.
| Transaction | M0_AXI_ARCACHE | M0_AXI_ARSNOOP |
|---|---|---|
| Read Barrier | 0010 | 0000 |
| Transaction | M0_AXI_AWCACHE | M0_AXI_AWSNOOP |
|---|---|---|
| Write Barrier | 0011 | 000 |
Incoming transactions on slave ports, cache maintenance operation on the Ctrl port as well as the current cache line state determines the kind of transactions that will be seen on the Master ACE interface. The following tables show all types of events. Some of the write related events actually appear on the master read channel.
| Event | Transaction | M0_AXI_ARCACHE | M0_AXI_ARSNOOP |
|---|---|---|---|
| Read Miss not Allocating | ReadOnce | 1111 | 0000 |
| Read Miss Allocating | ReadShared | 1111 | 0001 |
| Read Hit (any type) | No bus event | ||
| Write Miss Allocating | ReadUnique | 1111 | 0111 |
| Write Hit Shared | CleanUnique | 1111 | 1011 |
| Event | Transaction | M0_AXI_AWCACHE | M0_AXI_AWSNOOP |
|---|---|---|---|
| Write Miss not Allocating | WriteUnique | 0011 | 000 |
| Evicting Dirty Line 1 | WriteBack | 0011 | 011 |
| Write Hit Unique | No bus event | ||
|
|||