The optional Statistics and Control block can be used to collect cache
statistics such as cache hit rate and access latency. The statistics are primarily
intended for internal Xilinx use, but can also be
used to tailor the configuration of the System Cache core to meet the needs of a
specific application. The following types of statistics are collected:
- Port statistics for each slave interface
- Total Read and Write transaction counts
- Port queue usage for the six transaction queues associated with each port
- Cache hit rates for read and write
- Read and Write transaction latency
- Total ATC Read and Write transaction counts
- ATC TLB Address hit rates for read and write
- ATC TLB Read and write latency
- ATC TLB Read and write LRU replacement ratio
- Arbitration statistics
- Functional unit statistics
- Stall cycles
- Internal queue usage
- Port statistics for the master interface
- Read and write latency
- CCIX Backend
- Message count
- TLP count
- Credit count
- CHI Backend
- Message count
- Credit count
- ATS
- ATC Table Address hit rates for read and write
- ATC Table Read and write latency
- ATC Table Read and write LRW replacement ratio
- ATC Table PRI transaction Retry counts
- ATC Table PRI transaction TimeOut counts
- ATC Table TA transaction Fail counts
- ATC Table Invalidation transaction counts