AXI Master - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)
Document ID
PG118
Release Date
2021-11-05
Version
5.0 English

In a typical system with one MicroBlaze™ processor, as shown in the following figures, the instruction and data cache interfaces (M_AXI_IC and M_AXI_DC) are connected to dedicated AXI4 interfaces optimized for MicroBlaze on the System Cache core. The System Cache core often makes it possible to reduce the MicroBlaze internal cache sizes without reducing system performance. Non-MicroBlaze AXI4 interface masters are connected to one or more of the generic AXI4 slave interfaces of the System Cache core either through an AXI4 interconnect or directly as shown in the following figures.

Figure 1. Typical System with a Single Processor
Figure 2. Typical System with a Single Processor System Cache Page-1 Process System Cache System Cache Process.2 Memory Controller MemoryController Text Arrow S0_AXI S0_AXI Standard Arrow.495 M0_AXI M0_AXI Process.492 MicroBlaze MicroBlaze 8pt. Arial Text.11 M_AXI_DC M_AXI_DC Text Arrow.12 S1_AXI S1_AXI 8pt. Arial Text.13 M_AXI_IC M_AXI_IC Sheet.11 SO_AXI_GEN SO_AXI_GEN Sheet.12 Sheet.13 Sheet.14 Sx_AXI_GEN Sx_AXI_GEN Sheet.15 X17758-082416 X17758-082416
Figure 3. System without Processor

The System Cache core has 16 cache interfaces optimized for MicroBlaze, enabling direct connection of up to eight MicroBlaze processors, as shown in the following figure.

Figure 4. Typical System with Multiple MicroBlaze Processors