With ACE Master Port Cache Coherency - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

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5.0 English

When master port cache coherency is enabled the System Cache core is only coherent to the caches in the APU. Other masters such as the R5 real time processors need to use customary cache maintenance actions to ensure that they can see data from the coherent domain when required. This includes operations on its own caches, as well as ensuring that all dirty data has been moved downstream to the final destination in order to be visible.