Control Registers - 5.0 English

Table 1. Control Register Address Map
Offset	Register Name	Access	Format	Description
0x1_C000	Command	R/W	COMMAND	Command register
0x1_C008	StatEn	W	STATEN	Statistics Enable
0x1_C010	CMONonSecClean	W	CMOADDR	CMO - NonSecure Clean
0x1_C018	CMONonSecFlush	W	CMOADDR	CMO - NonSecure Flush
0x1_C020	Version0	R	VERSION0	Version Register 0, Basic
0x1_C024	Version1	R	VERSION1	Version Register 1, Extended
0x1_C030	DVMNonSecFirst	W	DVMDATA	DVM - NonSecure First Beat
0x1_C038	DVMNonSecSecond	W	DVMDATA	DVM - NonSecure Second Beat
0x1_C040	CMONonSecMem	W	CMOADDR	Barrier - NonSecure Memory
0x1_C048	CMONonSecSynch	W	CMOADDR	Barrier - NonSecure Synchronization
0x1_C050	CMOSecClean	W	CMOADDR	CMO - Secure Clean
0x1_C058	CMOSecFlush	W	CMOADDR	CMO - Secure Flush
0x1_C060	DVMSecFirst	W	DVMDATA	DVM - Secure First Beat
0x1_C068	DVMSecSecond	W	DVMDATA	DVM - Secure Second Beat
0x1_C070	CMOBarSecmem	W	CMOADDR	Barrier - Secure Memory
0x1_C078	CMOBarSecSynch	W	CMOADDR	Barrier - Secure Synchronization
0x1_C080	CMOSecCleanSh	W	CMOADDR	CMO - Secure CleanShared
0x1_C088	CMONonSecClnSh	W	CMOADDR	CMO - NonSecure CleanShared
0x1_C090	Reserved	W	CMOADDR	Reserved
0x1_C098	Reserved	W	CMOADDR	Reserved
0x1_C0C0	IRQStatus	R/W	IRQ	Interrupt Status
0x1_C0C8	IRQEnable	R/W	IRQ	Interrupt Enable
0x1_C0D0	IRQPending	R	IRQ	Interrupt Pending
0x1_C0E0	IntegCmd	R/W	INTEGCMD	Integrity Config - Scrub/Inject Command
0x1_C0E8	IntegInjectCfg	W	INTEGINJECTCFG	Integrity Config - Inject Configuration
0x1_C0F0	IntegScrub	R/W	INTEGSCRUB	Integrity Config - Scrub Timer
0x1_C100	IntegTagOnOff	R/W	INTEGONOFF	Integrity Status - Tag Integrity On/Off
0x1_C104	IntegTagStatus	R/W	INTEGSTATUS	Integrity Status - Tag Integrity Status
0x1_C108	IntegTagCECnt	R/W	INTEGERRCNT	Integrity Status - Tag CE Count
0x1_C10C	IntegTagUECnt	R/W	INTEGERRCNT	Integrity Status - Tag UE Count
0x1_C110	IntegTagCEFFA	R	INTEGFIRSTFAIL	Integrity Status - Tag CE First Failing Address
0x1_C118	IntegTagUEFFA	R	INTEGFIRSTFAIL	Integrity Status - Tag UE First Failing Address
0x1_C120	IntegDataOnOff	R/W	INTEGONOFF	Integrity Status - Data Integrity On/Off
0x1_C124	IntegDataStatus	R/W	INTEGSTATUS	Integrity Status - Data Integrity Status
0x1_C12C	IntegDataUECnt	R/W	INTEGERRCNT	Integrity Status - Data UE Count
0x1_C138	IntegDataFFA	R	INTEGFIRSTFAIL	Integrity Status - Data UE First Failing Address
0x1_C140	IntegATCOnOff	R/W	INTEGONOFF	Integrity Status - ATC Integrity On/Off
0x1_C144	IntegATCStatus	R/W	INTEGSTATUS	Integrity Status - ATC Integrity Status
0x1_C148	IntegATCCECnt	R/W	INTEGERRCNT	Integrity Status - ATC CE Count
0x1_C150	IntegATCFFA	R	INTEGFIRSTFAIL	Integrity Status - ATC CE First Failing Address

COMMAND Register

The Command register is primarily used for full cache events and some global setting. It provide the full cache manipulation functions, such as FCMakeInvalid to make sure the full cache is made invalid. When FCMakeInvalid or FCCleanInvalid is commanded and the corresponding configuration bit MakeInvalid or CleanInvalid is set, the external signal Initializing is asserted during the operation.

For the soft reset feature all bits should be set at the same time even if there are separate ones for major modules.

Note: When using commands to initialize the full cache, all traffic on the external interfaces should be quiescent.

Figure 1. COMMAND Register

Table 2. COMMAND Register Bit Definitions
Bits	Name	Reset Value	Access	Description
63:18				Reserved
17	AtomSnpMe	-	W	Atomic SnpMe Attribute is set regardless of transaction and state evaluation. CCIX/CHI specific.
16	AlwaysTryWrite	-	W	AlwaysTryWrite, always try to push data downstream to the memory (try using WriteEvictFull). CCIX specific.
15	FCWriteClean	-	W	Full Cache WriteClean class (remove dirty data using WriteCleanFull). Dirty lines always goes to SC state. CCIX/CHI specific.
14	CacheCMOStatus	-	W	Cache Maintenance Operations or initalization status (set while initialization or full cache is being invalidated)
13	StatReset	-	W	Statistics Reset
12	CleanInvalid	0	R/W	Soft CleanInvalid seen as initialization. CCIX/CHI specific.
11	MakeInvalid	0	R/W	Soft MakeInvalid seen as initialization. CCIX/CHI specific.
10	FCCleanInvalid	-	W	Full Cache CleanInvalid class, dirty data is written. CCIX/CHI specific.
9	FCMakeInvalid	-	W	Full Cache MakeInvalid class. CCIX/CHI specific.
8				Reserved
7:5	CMOMemAttr	-	W	Cache Maintenance Operations (CMO) Memory Attributes. CCIX specific.
4	CtrlRst	-	W	Soft Control Register Reset
3	ATSRst	-	W	Soft ATS Reset
2	BERst	-	W	Soft Back End (BE) Reset
1	CCRst	-	W	Soft Cache Core (CC) Reset
0	FERst	-	W	Soft Front End (FE) Reset

Statistics Enable Register, STATEN

Figure 2. Statistics Enable Register, STATEN

Table 3. Statistics Enable Register, STATEN, Bit Definitions
Bits	Name	Reset Value	Access	Description
63:1				Reserved
0	Enable	-	W	Statistics Enable

CMO -Address Register, CMOADDR

Register used for Cache Maintenance Commands. Before a CMO operation is issued, the traffic should be quiesced to avoid conflicts, thus the core CCIX/CHI traffic will be in idle when the CMO operation is performed.

Figure 3. CMO - Address Register, CMOADDR

Table 4. CMO Address Register, CMOADDR, Bit Definitions
Bits	Name	Reset Value	Access	Description
63:0		-	W	Cache Maintenance Operations (CMO) Address

Version Register 0, VERSION0

Figure 4. Version Register 0, VERSION0

Table 5. Version Register 0, VERSION0, Bit Definitions
Bits	Name	Reset Value	Access	Description
63:62				Reserved
61				Reserved
60:59				Reserved
58				Reserved
57				Reserved
56	EnInterrupt	C_ENABLE_INTERRUPT	R	Enable Interrupt
55				Reserved
54:53				Reserved
52:51	EnATS	C_ENABLE_ADDRESS_TRANSLATION	R	Enable Address Translation
50:49				Reserved
48:47	EnCCIX	C_ENABLE_CCIX_PROTOCOL	R	Enable CCIX protocol
46:45	EnACE	C_ENABLE_ACE_PROTOCOL	R	Enable ACE protocol
44:42				Reserved
41:39				Reserved
38:36	NoOfMasters	C_NUM_MASTER_PORTS	R	Number of Masters
35:34	EnNonSecure	C_ENABLE_NON_SECURE	R	Enable Security Handling
33:32	EnErr	C_ENABLE_ERROR_HANDLING	R	Enable Error Handling
31:30	EnVersion	C_ENABLE_VERSION_REGISTER	R	Version registers available: 0 - Basic register set, only this register 1 - Full register set, this and register1, see Version Register 1 Bit Field Definition. 2 and 3 are reserved
29:25	NoOfGenPort	C_NUM_GENERIC_PORTS	R	Generic Number of generic port implemented: 0 - All disabled 1 to 16 - Number of ports implemented 17 to 31 are reserved
24:20	NoOfOptPort	C_NUM_OPTIMIZED_PORTS	R	Number of optimized port implemented: 0 - All disabled 1 to 16- Number of ports implemented 17 to 31 are reserved
19:18	InExcl	C_ENABLE_EXCLUSIVE	R	Internal Exclusive monitor implementation: 0 - Disabled 1 - Enabled 2 to 3 are reserved
17:16	EnCoher	C_ENABLE_COHERENCY	R	Cache coherency implementation: 0 - Disabled 1 - Optimized port cache coherency 2 - Master port cache coherency 3 - reserved
15:8	EnStat	C_ENABLE_STATISTICS	R	Enabled statistics block, binary encoded with multiple selected simultaneously: xxxx_xxx1 - Optimized ports xxxx_xx1x - Generic port xxxx_x1xx - Arbiter xxxx_1xxx - Access xxx1_xxxx - Lookup xx1x_xxxx - Update x1xx_xxxx - Backend 1xxx_xxxx - ATC
7:0	Version	15	R	Core Version: 0 - System Cache version 2.00a 1 - System Cache version 3.0 2 - System Cache version 2.00b 3 - System Cache version 3.1 4 - System Cache version 4.0 5-7 - Reserved 8 - System Cache version 5.0 9 - System Cache version 5.0.1 10 - System Cache version 5.0.2 11 - System Cache version 5.0.3 12 - System Cache version 5.0.4 13 - System Cache version 5.0.5 14 - System Cache version 5.0.6 15 - System Cache version 5.0.7 16-255 Reserved

Version Register 1, VERSION1

Figure 5. Version Register 1, VERSION1

Table 6. Version Register 1, VERSION1, Bit Definitions
Bits	Name	Reset Value	Access	Description
63:56				Reserved
55:53				Reserved
52				Reserved
51:40	Freq	C_FREQ/1000000	R	Frequency in MHz
39:38				Reserved
37:36				Reserved
35:30				Reserved
29				Reserved
28:26				Reserved
25:23				Reserved
22:19	LxCacheLineLen	Log2(C_Lx_CACHE_LINE_LENGTH/4)	R	Cache line length of connected masters on the optimized port, see Cache Line Length Definitions below.
18:15	LxCacheSize	Log2(C_Lx_CACHE_SIZE/64)	R	Cache size of connected masters on the optimized port, see Cache Size below.
14:11	CacheLineLen	Log2(C_CACHE_LINE_LENGTH/4)	R	Internal cache line length, see Cache Line Length Definitions below.
10:6	CacheSize	Log2(C_CACHE_SIZE/64)	R	Internal cache size, see Cache Size below.
5:3	CacheDWidth	Log2(C_CACHE_DATA_WIDTH/2)	R	Internal cache data width: 0 - 8-bit data interface and path 1 - 16-bit data interface and path 2 - 32-bit data interface and path 3 - 64-bit data interface and path 4 - 128-bit data interface and path 5 - 256-bit data interface and path 6 - 512-bit data interface and path 7 - 1024-bit data interface and path
2:0	Ways	Log2(C_NUM_WAYS/2)	R	Number of associative sets: 0 = 2-way set associative 1 = 4-way set associative 2 to 7 = Reserved

Table 7. Cache Size
Value	Description	Value	Description
0	64 byte cache size	9	32K byte cache size
1	128 byte cache size	10	64K byte cache size
2	256 byte cache size	11	128K byte cache size
3	512 byte cache size	12	256K byte cache size
4	1K byte cache size	13	512K byte cache size
5	2K byte cache size	14	1M byte cache size
6	4K byte cache size	15	2M byte cache size
7	8K byte cache size	16	4M byte cache size
8	16K byte cache size	17 - 31	Reserved

Table 8. Cache Line Length Definitions
Value	Description	Value	Description
0	4 word cache line	5	128 word cache line
1	8 word cache line	6	256 word cache line
2	16 word cache line	7	512 word cache line
3	32 word cache line	8	1024 word cache line
4	64 word cache line	9 - 15	Reserved

DVM Data Register, DVMDATA

Distributed Virtual Memory (DVM) messages are only available with Master ACE Coherency. Any arbitrary DVM message, single or two part, can be insert with the DVM register functionality. The format is described in the AMBA AXI and ACE Protocol Specification in the "Distributed Virtual Memory Transactions" chapter.

The insertion is triggered by writing to DVMNonSecFirst or DVMSecFirst, i.e. for a two part message it is required that the second part is written before the first to make sure it is available when message generation is triggered by writing the first part.

Table 9. DVM Data Register Bit Definitions
Bits	Name	Reset Value	Access	Description
n-1:0	"Various"		W	Encoding depends on DVM message, see AMBA AXI and ACE Protocol Specification

IRQ Status Register

Figure 6. IRQ Status Register

Table 10. IRQ Status Register Bit Definitions
Bits	Name	Reset Value	Access	Description
63:60				Reserved
59:56			R/W	SAM S3 to S0 interrupt status. Write 1 to acknowledge an interrupt. 56 - S0, SAM no match 59:57 - S3 to S1, Reserved
55:51				Reserved
50:32	Backend	0	R/W	Backend B18 to B0 interrupt status. Write 1 to acknowledge an interrupt. 37:32 - B5 to B0, Reserved 38 - B6, Comp/CompData with DatErr/NonDatErr (HA response tagged with Data or Non-Data Error) 50:39 - B18 to B7, Reserved
31:23				Reserved
22:16	Core	0	R/W	Core C6 to C0 interrupt status. Write 1 to acknowledge an interrupt. 16 - C0, Tag CE 17 - C1, Tag UE 18 - C2, Data Miss Clean/Dirty CE 19 - C3, Data Hit Clean/Dirty CE 20 - C4, Data Miss Clean/Dirty UE 21 - C5, Data Hit Clean UE 22 - C6, Data Hit Dirty UE
15				Reserved
14:8	Translation	0	R/W	Translation T6 - T0 interrupt status. Write 1 to acknowledge an interrupt. 13:8 - T5 to T0, Reserved 14 - T6, ATS Table Address, Page, PASID CE
7:1				Reserved
0	Frontend	0	R/W	Frontend F0 interrupt status. Write 1 to acknowledge an interrupt. 0 - F0, Reserved

IRQ Enable Register

Figure 7. IRQ Enable Register

Table 11. IRQ Enable Register Bit Definitions
Bits	Name	Reset Value	Access	Description
63:0	IRQ Enable	0	R/W	Enable interrupts. All bit positions are mapped to the corresponding positions in the IRQ Status Register.

IRQ Pending Register

Figure 8. IRQ Pending Register

Table 12. IRQ Pending Register Bit Definitions
Bits	Name	Reset Value	Access	Description
63:0	IRQ Pending		R	Pending interrupts. All bit positions are mapped to the corresponding positions in the IRQ Status Register.

Integrity Config Scrub/Inject Command Register, INTEGCMD

Figure 9. Integrity Config Scrub/Inject Command Register, INTEGCMD

Table 13. Integrity Config Scrub/Inject Command Register Bit Definitions
Bits	Name	Reset Value	Access	Description
31	InjectCache	0	R/W	Inject Pending Cache Fault pattern
30	ScrubATC	0	R/W	Scrub ATC
29	InjectATC	0	R/W	Inject Pending ATC Fault
28:16				Reserved
15:0	RAMIndex	0	R/W	Scrub/Inject RAM Index

Integrity Config Inject Configuration Register, INTEGINJECTCFG

Figure 10. Integrity Config Inject Configuration Register, INTEGINJECTCFG

Table 14. Integrity Config Inject Configuration Register Bit Definitions
Bits	Name	Reset Value	Access	Description
31	ClearInj	-	W	Clear Inject Fault pattern
30:24				Reserved
23	InjFaultType	-	W	Inject Fault Type: 0 - Information bit (actual data or tag contents) 1 - Integrity (actual extra bits for ECC or parity)
22:20	InjGrp	-	W	Inject Group 0 - Tag 1 - Data 2 - ATC 3-7 - Reserved
19:16	InjWayPos	-	W	Inject Way Position (number of Way in Set)
15:10	InjBlkPos	-	W	Inject Block Position (block position within cache line)
9:0	InjBitPos	-	W	Inject Bit Position (bit position within a block)

Integrity Config Scrub Timer Register, INTEGSCRUB

Figure 11. Integrity Config Scrub Timer Register, INTEGSCRUB

Table 15. Integrity Config Scrub Timer Register Bit Definitions
Bits	Name	Reset Value	Access	Description
31	ScrubOnOff	1	R/W	Scrubbing: 0 - Off 1 - On
30:20				Reserved
19:0	ScrubCntVal	0XFFFFF	R/W	Scrubbing Event Counter Value (Number of clock cycles until scrubbing next RAM Index)

Integrity On/Off Register, INTEGONOFF

Figure 12. Integrity On/Off Register, INTEGONOFF

Table 16. Integrity On/Off Register Bit Definitions
Bits	Name	Reset Value	Access	Description
31:1				Reserved
0	IntegOnOff	1	R/W	Integrity: 0 - Off 1 - On

Integrity Status Register, INTEGSTATUS

Figure 13. Integrity Status Register, INTEGSTATUS

Table 17. Integrity Status Register Bit Definitions
Bits	Name	Reset Value	Access	Description
31:2				Reserved
1	CE	0	R/W	Correctable Error Status
0	UE	0	R/W	Uncorrectable Error Status

Integrity Error Count Register, INTEGERRCNT

Figure 14. Integrity Error Count Register, INTEGERRCNT

Table 18. Integrity Error Count Register Bit Definitions
Bits	Name	Reset Value	Access	Description:
31:16				Reserved
15:0	ErrCnt	0	R/W	Error Count, either correctable or uncorrectable depending on type

Integrity First Fail Register, INTEGFIRSTFAIL

Figure 15. Integrity First Fail Register, INTEGFIRSTFAIL

Table 19. Integrity First Fail Register Bit Definitions
Bits	Name	Reset Value	Access	Description
63:0	FFA	0		First Failing Address, physical address or ATC table entry