Complete CHI Transaction Flow - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)
Document ID
PG118
Release Date
2021-11-05
Version
5.0 English

Like ACE Master Port coherency CHI relies on AxCACHE and the cache state to determine the resulting events in the CHI domain.

Table 1. Complete Slave ARCACHE to Cache Event and Potential CHI Transaction Mapping
Slave ARCACHE Cache Event Cache Action CHI Transaction
00xx Read Miss Bypass Cache ReadNoSnp MemAttr=Device-nRnE

MemAttr=Device-nRE

MemAttr=Non-Cacheable
Read Hit Use cached line N/A N/A
x100

x110

 Read Miss Bypass cache ReadOnce MemAttr=Snoopable WriteBack No-Allocate
Read Hit Use cached line N/A N/A
0101

0111

 Read Miss Allocate cache line and forward data ReadShared MemAttr=Snoopable WriteBack Allocate
Read Hit Use cached line N/A N/A
1101

1111

 Read Miss Allocate cache line and forward data ReadUnique MemAttr=Snoopable WriteBack Allocate
Read Hit Use cached line N/A N/A
10xx Read Miss Bypass cache ReadOnce MemAttr=Snoopable WriteBack No-Allocate
Read Hit Use cached line N/A N/A
Table 2. Complete Slave AWCACHE to Cache Event and Potential CHI Transaction Mapping
Slave AWCACHE Cache Event Cache Action CHI Transaction
00xx Write Miss Bypass cache WriteUniquePtl MemAttr=Snoopable WriteBack No-Allocate
Write Hit Shared Request write permission, evict dirty cache line after write CleanUnique WriteBackFull MemAttr=Snoopable WriteBack Allocate
Write Hit Unique Evict dirty cache line after write WriteBackFull  

0100

0101

0110

 Write Miss Bypass cache WriteUniquePtl MemAttr=Snoopable WriteBack No-Allocate
Write Hit Shared Request write permission, evict dirty cache line after write CleanUnique WriteBackFull MemAttr=Snoopable WriteBack No-Allocate
Write Hit Unique Evict dirty cache line after write WriteBackFull MemAttr=Snoopable WriteBack No-Allocate
0111 Write Miss Bypass cache WriteUniquePtl ReqAttr=WBA
Write Hit Shared Request write permission CleanUnique MemAttr=Snoopable WriteBack No-Allocate
Write Hit Unique Update cache line N/A N/A

1x00

1x01

1x10

 Write Miss Bypass cache WriteUniquePtl MemAttr=Snoopable WriteBack Allocate
Write Hit Shared Request write permission, evict dirty cache line after write CleanUnique WriteBackFull MemAttr=Snoopable WriteBack Allocate
Write Hit Unique Evict dirty cache line after write WriteBackFull MemAttr=Snoopable WriteBack Allocate
1x11 Write Miss Allocate cache line ReadUnique MemAttr=Snoopable WriteBack Allocate
Write Hit Shared Request write permission CleanUnique MemAttr=Snoopable WriteBack Allocate
Write Hit Unique Update cache line N/A N/A