AXI Memory Properties - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

Document ID: PG118
Release Date: 2021-11-05
Version: 5.0 English

The following tables show the ARCACHE and AWCACHE bus contents for Read and Write channels respectively, according to the AMBA® AXI and ACE Protocol Specification.

Table 1. ARCACHE Bit Field
Other Allocate	Read Allocate	Modifiable	Bufferable
3	2	1	0

Table 2. AWCACHE Bit Field
Write Allocate	Other Allocate	Modifiable	Bufferable
3	2	1	0