To handle several AXI4 masters in a system two methods are available: either an AXI4 interconnect is used to share the single generic AXI4 slave interface on the System Cache core or, alternatively, multiple generic AXI4 interfaces are used (most commonly one per master that needs access). The generic AXI4 interface has a configurable data width to efficiently match the connected AXI4 masters. This ensures that both the system area and the AXI4 access latency are reduced.
The generic AXI4 slave interface is compliant to the full AXI4 interface specification. The interface includes the subsequent features and exceptions:
- Support for 32-, 64-, 128-, 256-, and 512-bit data widths
- Support for all burst types and sizes
- No support for FIXED bursts
- Up to 16 beats for WRAP bursts
- Up to 256 beats for INCR burst
- Optional support for Secure/Non-Secure handling
- Exclusive accesses are treated as a normal accesses, never returning EXOKAY, unless the internal exclusive monitor is enabled
- Support for burst sizes that are less than the data width (narrow bursts)
- AXI4 user signals are supported with CCIX Master Coherency enabled, to provide atomic transactions
- Out-of-order transactions based on thread ID value are supported with CCIX Master Coherency enabled. Otherwise all transactions are executed in order regardless of thread ID value, and no read reordering or write reordering is implemented.