MicroBlaze Processor Optimized ACE Slave Interface - 5.0 English

The optimized AXI4 interfaces are replaced by ACE point-to-point connections when cache coherency is enabled. They are optimized for accesses performed by the cache interfaces on the MicroBlaze™ processor. Eight MicroBlaze processors are supported with coherency enabled.

The Optimized ACE slave interfaces are compliant to a subset of the ACE interface specification. The interface includes the subsequent features and exceptions:

• Support for 32-bit data width
• Support for some ACE burst types and sizes
  • No support for FIXED bursts
  • Optional support for Secure/Non-Secure handling
  • Only sharable transactions are supported
  • WRAP bursts corresponding to the WRAP bursts corresponding to the MicroBlaze™ processor cache line length (either 4, 8, or 16 beats) processor cache line length (either 4, 8, or 16 beats)
  • Single beat INCR burst, or either 4, 8, or 16 beats corresponding to the MicroBlaze™ processor cache line length
  • The AR channel supports ReadOnce, ReadClean, CleanUnique, CleanInvalid, MakeInvalid and DVM transactions
  • Support for propagation of CleanInvalid and MakeInvalid to peer or downstream caches
  • The AW channel supports WriteUnique only
  • Exclusive accesses are only supported for sharable transactions (with ACE transactions exchange)
  • Only support for native transaction size bursts (same as data width for the port). Single beat support for all sizes
  • The AC channel can generate ReadClean, ReadOnce, CleanUnique, CleanInvalid, MakeInvalid and DVM transactions
  • CD channel data is not used
• Only support for burst transactions that are contained within a single cache line in the System Cache core
• Only support for Write-Through cache in the MicroBlaze™ processor
• AXI4 user signals are not supported
• All transactions executed in order regardless of thread ID value. No read reordering or write reordering is implemented.