The System Cache core adheres to:
- AMBA® AXI4 and ACE interface standard (see Arm® AMBA AXI Protocol Specification, Version 2.0 ARM IHI 0022E)
- AMBA AXI4-Stream interface standard (see Arm AMBA 4 AXI4-Stream Protocol Specification, Version 1.0 ARM IHI 0051A)
- AMBA® CHI interface standard (see AMBA® 5 CHI Architecture Specification, Issue B ARM IHI 0050B)
- AMBA CXS interface standard (see Arm AMBA CXS Protocol Specification, ARM IHI 0079A)
- CCIX Cache Coherent Interconnect for Accelerators standard (see CCIX Base Specification Revision 1.1 Version 1.0)
- PCI Express® standard (see PCI Express Base Specification Revision 5.0 Version 1.0)
- PCI Express ATS Memory Attributes (see ATS Memory Attributes ECN, Revision A)