Non-Secure Handling - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

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5.0 English

The optional handling of Secure/Non-Secure can be enabled with the C_ENABLE_NON_SECURE parameter. When active the AxPROT[1] bit is treated as an extra address bit to provide a distinction between the two modes. This also means that the same address can be cached as both Secure and Non-Secure at the same time.

Additional control registers are available when this feature is enabled to allow command and control of the System Cache core, distinguishing between the different modes.

Note: When enabling Address Translation, the same Host TA Address map will be used. The need to keep a unique mapping per mode must be resolved on the system level in host TA, by invalidation and address remapping.