Parameter Values - 5.0 English

Certain parameters are only available in some configurations, others impose restrictions that IP cores connected to the System Cache core need to adhere to. All these restrictions are enforced by design rule checks to guarantee a valid configuration. The following tables describe the System Cache core parameters.

The parameter restrictions are:

• Internal cache data width must either be 32 or a multiple of the cache line length of masters connected to the optimized ports (C_CACHE_DATA_WIDTH = 32 or C_CACHE_DATA_WIDTH = n * 32 * C_Lx_CACHE_LINE_LENGTH).
• All optimized slave port data widths must be less than or equal to the internal cache data width (C_Sx_AXI_DATA_WIDTH ≤ C_CACHE_DATA_WIDTH).
• All generic slave port data widths must be less than or equal to the internal cache data width (C_Sx_AXI_GEN_DATA_WIDTH ≤ C_CACHE_DATA_WIDTH).
• The master port data width must be greater then or equal to the internal cache data width (C_CACHE_DATA_WIDTH ≤ C_M_AXI_DATA_WIDTH).
• The internal cache line length must be greater than or equal to the corresponding cache line length of the AXI4 masters connected to the optimized port (C_CACHE_LINE_LENGTH ≥ C_Lx_CACHE_LINE_LENGTH).

• With optimized port cache coherency enabled, only 32-bit data is supported for all parts of the datapath.

  (C_Sx_AXI_DATA_WIDTH = C_CACHE_DATA_WIDTH = C_M_AXI_DATA_WIDTH = 32).

• With master port cache coherency, data widths are limited to 128 (C_Sx_AXI_DATA_WIDTH ≤ C_CACHE_DATA_WIDTH = C_M_AXI_DATA_WIDTH = 128).