Backend ATS Registers - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)
Document ID
PG118
Release Date
2021-11-05
Version
5.0 English

Backend ATS Address Map

In the nominal use case with CHI or CCIX protocol context the following registers are handled by firmware executing in the MicroBlaze processor sub-system, and there is nothing the user needs to handle.

Table 1. Backend ATS Address Map
Offset Register Name Format Description
0x1_9800 PASIDATSEXTCAP 64 PASID & ATS Extended Capability Header

Note: Currently unused, the external processor handles PCIe configuration in FW.
0x1_9808 PASIDATSCAP 64 PASID & ATS Capability Header
0x1_9810 ATSPAGEREQCAP 64 ATS Outstanding Page Request Capacity
0x1_9818 ATSPAGEREQALL 64 ATS Outstanding Page Request Allocation
0x1_9820 ATSPRICTRL 64 ATS & PRI Control
0x1_9828 PASIDCTRL 64 PASID Control
0x1_9840 ATSPAGEREQSTAT 64 ATS Page Request Status
0x1_9860 ATSPCIECTRL 64 ATS PCIe Control
0x1_9870 ATSPCIEEXTCTRL 64 ATS PCIe Extended Control

PASID & ATS Extended Capability Header Register

This register holds the System Cache PCIe configuration capabilities. Firmware replaces this information with locally defined PCIe endpoint capabilities.

Figure 1. PASID & ATS Extended Capability Header Register System Cache Page-1 Sheet.32 Sheet.23 Sheet.3 0 0 Sheet.13 Sheet.24 15 15 Sheet.27 16 16 Sheet.31 Sheet.48 31 31 Sheet.98 Sheet.99 Sheet.100 Sheet.101 32 32 Sheet.102 Sheet.103 47 47 Sheet.104 48 48 Sheet.105 Sheet.106 51 51 Sheet.107 52 52 Sheet.108 Sheet.109 63 63 Sheet.110 Reserved Reserved Sheet.112 CAPVER CAPVER Sheet.113 PASIDECID PASIDECID Sheet.115 ATSECID ATSECID Sheet.116 PRIECID PRIECID Sheet.1 X20736-073019 X20736-073019
Table 2. PASID & ATS Extended Capability Header Bit Definitions
Bits Name Reset Value Access Description
63:52       Reserved
51:48 CAPVER 0 R Capability version
47:32 PASIDECID 0 R PASID Extended Capability ID
31:16 PRIECID 0 R PRI Extended Capability ID
15:0 ATSCID 0 R PASID & ATS Extended Capability Header ID

PASID & ATS Capability Header Register

This register holds the System Cache PCIe PASID and ATS configuration capabilities. Firmware reads this information and combines it into a System Cache capabilities PCIe Configuration response.

Note: System Cache uses bit 7 for MEMATTR as originally proposed in earlier PCI Express ATS expansions, whereas the PCI Express Base Specification Revision 5.0 Version 1.0 implies that bit 8 should be used – as bit 7 is used for Relaxed Ordering Supported (not used by System Cache) in the PCI Express specification.
Figure 2. PASID & ATS Capability Header Register System Cache Page-1 Sheet.107 Sheet.95 Sheet.71 Sheet.62 Sheet.47 Sheet.5 Sheet.3 0 0 Sheet.6 4 4 Sheet.7 Sheet.8 Sheet.9 5 5 Sheet.10 Sheet.11 Sheet.12 6 6 Sheet.13 Sheet.15 7 7 Sheet.31 Sheet.48 32 32 Sheet.50 Sheet.51 33 33 Sheet.52 Sheet.53 Sheet.54 34 34 Sheet.55 Sheet.57 35 35 Sheet.61 Sheet.63 39 39 Sheet.66 40 40 Sheet.70 Sheet.72 44 44 Sheet.75 45 45 Sheet.85 Sheet.96 63 63 Sheet.98 Reserved Reserved Sheet.99 PASIDMW PASIDMW Sheet.100 Reserved Reserved Sheet.101 PRIVMD PRIVMD Sheet.102 EXECP EXECP Sheet.103 Reserved Reserved Sheet.104 GLOBALINVAL GLOBALINVAL Sheet.105 PAGEALIGN PAGEALIGN Sheet.106 INVALIDQD INVALIDQD Sheet.108 8 8 Sheet.109 MEMATTR MEMATTR Sheet.110 Sheet.1 X20737-073019 X20737-073019
Table 3. PASID & ATS Capability Header Bit Definitions
Bits Name Reset Value Access Description
63:45       Reserved
44:40 PASIDMW 0x14 R Max PASID Width (Used when CHI PASID enabled)
39:35       Reserved
34 PRIVMD 0 R Privileged Mode Supported (Used when CHI PASID enabled)
33 EXECP 0 R Execute Permission Supported (Used when CHI PASID enabled)
32:8       Reserved
7 MEMATTR 1 R Memory Attributes Supported
6 GLOBALINVAL 1 R Global Invalidate Supported (Used when CHI PASID enabled)
5 PAGEALIGN 1 R Page Align Request
4:0 INVALIDQD 1 R Invalidate Queue Depth

ATS Outstanding Page Request Capacity Register

This register holds the System Cache ATS PRG configuration capabilities. Firmware reads this information and combines it into a System Cache capabilities PCIe Configuration response.

Figure 3. ATS Outstanding Page Request Capacity Register System Cache Page-1 Sheet.2 Sheet.5 Sheet.7 0 0 Sheet.17 Sheet.18 31 31 Sheet.20 32 32 Sheet.29 Sheet.33 63 63 Sheet.35 Reserved Reserved Sheet.38 ATSOPRC ATSOPRC Sheet.1 X20738-073019 X20738-073019
Table 4. ATS Outstanding Page Request Capacity Bit Definitions
Bits Name Reset Value Access Description
63:32       Reserved
31:0 ATSOPRC 0xF R ATS Outstanding Page Request Capacity

ATS Outstanding Page Request Allocation Register

This register holds the System Cache ATS PRG Allocation. Firmware writes this information during configuration, but it is allowed to be changed after System Cache initialization.

Figure 4. ATS Outstanding Page Request Allocation Register System Cache Page-1 Sheet.2 Sheet.3 Sheet.4 0 0 Sheet.5 Sheet.6 31 31 Sheet.7 32 32 Sheet.8 Sheet.9 63 63 Sheet.10 Reserved Reserved Sheet.11 ATSOPRA ATSOPRA Sheet.1 X20739-073019 X20739-073019
Table 5. ATS Outstanding Page Request Allocation Bit Definitions
Bits Name Reset Value Access Description
63:32       Reserved
31:0 ATSOPRA 0 R/W ATS Outstanding Page Request Allocation

ATS & PRI Control Register

This register holds the System Cache ATS and PRI control. Firmware writes this information during configuration, but it is allowed to be changed after System Cache initialization.

If ATS Enable is changed from 0 to 1, a silent complete invalidation of the ATC Table is performed.

Figure 5. ATS & PRI Control Register System Cache Page-1 Sheet.112 Sheet.107 Sheet.95 Sheet.47 Sheet.23 Sheet.8 Sheet.3 0 0 Sheet.7 Sheet.9 4 4 Sheet.12 5 5 Sheet.19 Sheet.24 14 14 Sheet.26 Sheet.27 15 15 Sheet.28 Sheet.30 16 16 Sheet.40 Sheet.48 31 31 Sheet.50 Sheet.51 32 32 Sheet.52 Sheet.53 Sheet.54 33 33 Sheet.55 Sheet.57 34 34 Sheet.76 Sheet.96 63 63 Sheet.98 Reserved Reserved Sheet.99 Reserved Reserved Sheet.100 Reserved Reserved Sheet.101 PRIRES PRIRES Sheet.102 PRIEN PRIEN Sheet.103 ATSEN ATSEN Sheet.104 ATSSTU ATSSTU Sheet.105 48 48 Sheet.106 47 47 Sheet.108 Sheet.109 PRIFailLoopCount PRIFailLoopCount Sheet.110 13 13 Sheet.113 Sheet.114 MEE MEE Sheet.1 X20740-073019 X20740-073019
Table 6. ATS & PRI Control Bit Definitions
Bits Name Reset Value Access Description
63:48 PRIFailLoopCount 0 R/W Fail Loop Count
47:34       Reserved
33 PRIRES 0 R/W PRI Reset
32 PRIEN 0 R/W PRI Enable
31:16       Reserved
15 ATSEN 0 R/W ATS Enable
14 MEE 0 R/W Mem Attributes Enable
13:5       Reserved
4:0 ATSSTU 0 R/W ATS Smallest Translation Unit

PASID Control Register

This register holds the System Cache PASID control. Firmware writes this information as a result of the PCIe enumeration and configuration phase. It should not be changed after System Cache initialization.

Figure 6. PASID Control Register System Cache Page-1 Sheet.95 Sheet.2 Sheet.3 0 0 Sheet.4 Sheet.5 Sheet.6 1 1 Sheet.7 Sheet.8 Sheet.9 2 2 Sheet.10 Sheet.12 3 3 Sheet.52 Sheet.96 63 63 Sheet.98 Reserved Reserved Sheet.129 PASIDEN PASIDEN Sheet.146 PASIDEPEN PASIDEPEN Sheet.147 PASIDPMEN PASIDPMEN Sheet.1 X20741-073019 X20741-073019
Table 7. PASID Control Bit Definitions
Bits Name Reset Value Access Description
63:3       Reserved
2 PASIDPMEN 0 R/W PASID Privilege Mode Enable (Valid in CHI PASID context, otherwise Reserved)
1 PASIEPEN 0 R/W PASID Execute Permission Enable (Valid in CHI PASID context, otherwise Reserved)
0 PASIDEN 0 R/W PASID Enable (Valid in CHI PASID context, otherwise Reserved)

ATS Page Request Status Register

This register holds the System Cache ATS PRG status. Firmware writes this information during configuration, but it is allowed to be changed after System Cache initialization.

Figure 7. ATS Page Request Status Register System Cache Page-1 Sheet.95 Sheet.32 Sheet.17 Sheet.2 Sheet.3 0 0 Sheet.4 Sheet.5 Sheet.6 1 1 Sheet.7 Sheet.9 2 2 Sheet.16 Sheet.18 7 7 Sheet.20 Sheet.21 8 8 Sheet.22 Sheet.24 9 9 Sheet.28 Sheet.33 14 14 Sheet.35 Sheet.36 15 15 Sheet.37 Sheet.39 16 16 Sheet.67 Sheet.96 63 63 Sheet.98 Reserved Reserved Sheet.99 Reserved Reserved Sheet.100 Reserved Reserved Sheet.101 ATSRESFAIL ATSRESFAIL Sheet.102 ATSUPRGI ATSUPRGI Sheet.103 ATSPRGRES ATSPRGRES Sheet.104 ATSSTOP ATSSTOP Sheet.1 X20742-073019 X20742-073019
Table 8. ATS Page Request Status Bit Definitions
Bits Name Reset Value Access Description
63:16       Reserved
15 ATSPRGRES 0 R PRG Response PASID Required (Valid in CHI PASID context, otherwise Reset Value)
14:9       Reserved
8 ATSSTOP 1 R PRG Stop
7:2       Reserved
1 ATSUPRGI 0 R/W Unexpected Page Request Group Index
0 ATSRESFAIL 0 R/W Response Failure

ATS PCIe Control Register

This register holds the System Cache ATS PCIe configuration control. Currently the system-level processor firmware writes this information as a result of the PCIe enumeration and configuration phase. It should not be changed after System Cache initialization.

Figure 8. ATS PCIe Control Register System Cache Page-1 Sheet.95 Sheet.77 Sheet.65 Sheet.47 Sheet.23 Sheet.3 0 0 Sheet.13 Sheet.24 15 15 Sheet.27 16 16 Sheet.34 Sheet.46 Sheet.48 23 23 Sheet.50 Sheet.51 24 24 Sheet.54 31 31 Sheet.57 32 32 Sheet.61 Sheet.66 42 42 Sheet.68 Sheet.69 43 43 Sheet.70 Sheet.72 44 44 Sheet.76 Sheet.78 47 47 Sheet.81 48 48 Sheet.91 Sheet.96 63 63 Sheet.98 Reserved Reserved Sheet.99 PCIEPBDF PCIEPBDF Sheet.100 PCIETAGLO PCIETAGLO Sheet.101 PCIETAGHI PCIETAGHI Sheet.102 PCIEMPS PCIEMPS Sheet.103 PCIETD PCIETD Sheet.104 PCIETABDF PCIETABDF Sheet.1 X20743-073019 X20743-073019
Table 9. ATS PCIe Control Bit Definitions
Bits Name Reset Value Access Description
63:48 PCIETABDF 0 R/W PCIe TA BDF, Root Complex BDF (used by ATS/CCIX)
47:44       Reserved
43 PCIETD 0 R/W PCIe TD, Optional ECRC Enable
42:32 PCIEMPS 0 R/W PCIe MPS, (used by ATS/CCIX)
31:24 PCIETAGHI 0xFF R/W PCIe 8bits Tag High, limited unique range if dual System Cache in EP
23:16 PCIETAGLO 0 R/W PCIe 8bits Tag Low
15:0 PCIEEPBDF 0 R/W PCIe EP BDF, (used by ATS/CCIX)

ATS PCIe Extended Control Register

This register holds the System Cache ATS PCIe Extended configuration control. Currently, the system level processor firmware writes this additional information as a result of the PCIe enumeration and configuration phase. The extended configuration allows none, partial, full, or enhanced selection of FunctionID for self identification. In addition to legacy EP BDF, the register captures EP FunctionID for EP identification – usage of EP BDF / EP FuntionID depends upon PCIEFUNCIDEN settings.

Optional 10 bits TAG support now enables System Cache to allow the 10 bits TAG option with Host capabilities support (PCIeRev4.0 onwards - System Cache present refer to PCIeRev5.0). With 10 bits TAG mode enabled, this register holds TAG Low and TAG High ranges for 10bits TAG, and supersedes 8bits TAG Low and TAG High ranges in ATS PCIe Control Register. Settings in this register should not be changed after System Cache initialization.

Note: System Cache expects selection by PCIEFUNCIDEN, to enable EPBDF override with FUNCTIONID/COMPONENTID - None/Partial/Full/Enhanced, based upon target technology. User firmware is expected to set PCIEFUNCIDEN, PCIEEPBDF and FUNCTIONID/COMPONENTID to the correct system values during the configuration phase. For backwards compatibility, PCIEFUNCIDEN with default Reset value, 0b00, will select the PCIEEPBDF settings.
Figure 9. ATS PCIe Extended Control Register
Table 10. ATS PCIe Extended Control Bit Definitions
Bits Name Reset Value Access Description
63:62 PCIEFUNCIDEN 0 R/W PCIe Function ID Enable, (used by ATS/CCIX)
  • 0b00 = Disable EP FUNCTIONID and COMPONENT ID, use EP BDF at all TLPs on Completer ID/Requester ID/Device ID PCIe Configuration register.
  • 0b01 = Enable EP Partial FUNCTIONID at TLPs on Completer ID/Requester ID, EP Self identification Device ID = EP BDF (PCIe Configuration register.
  • 0b10 = Enable EP FUNCTIONID at all TLPs on Completer ID/Requester ID/Device ID, EP BDF (PCIe Configuration register) and COMPONENT ID unused.
  • 0b11 = Reserved
61 PCIE10bTAGEN 0 R/W PCIe 10bit Tag Enable, (used by ATS/CCIX)
  • 0 = 8bit Tag – overloaded T9/T8 bits normal mode
  • 1 = Enable 10bit Tag extension on Completer and Requester Interface
60 PCIEPOISONREQEN 0 R/W

PCIe Poison Request Enable (extend the Poison control if 10bits TAG mode are supported, as field are consumed), (used by ATS/CCIX) bit unused in 8bits TAG mode

  • 0 = Disable Completer poison completion(CC) / Requester poison request(RQ) upon NonCorr Payload Error, if AER Disabled on CC/RQ
  • 1 = Enable Completer poison completion(CC) / Requester poison request(RQ) upon NonCorr Payload Error, if AER Enabled on CC/RQ
59:58       Reserved
57:48 PCIE10bTAGHIGH 0x3FF R/W PCIe 10bits Tag High, override 8bits Tag Low - if 10bit Tag Enable bit is set. Limited unique range if dual System Cache in EP
47:42       Reserved
41:32 PCIE10bTAGLOW 0 R/W PCIe 10bits Tag Low, override 8bits Tag Low - if 10bit Tag Enable bit is set
31:15       Reserved (EP BAR ID, PF# presence)
14:13 PCIEEPCID 0 R/W PCIe EP Component ID. Reserved - should always be set to 0.
12:0 PCIEEPFUNCID 0 R/W PCIe EP FunctionID, (used in partial/full and enhanced mode by ATS/CCIX)