CCIX Port Descriptions
The block diagram of the System Cache core configured for CCIX is shown in
the following figure. All interfaces are compliant to AXI4, AXI4-Stream or CXS where applicable. The input signals ACLK
and ARESETN
implement
clock and reset for the entire System Cache core.
Figure 1. CCIX Block Diagram
Name | Type | Description |
---|---|---|
ACLK | Input | Core clock |
ARESETN | Input | Synchronous reset of core |
Initializing | Output | Core is initializing after reset |
Sx_AXI_GEN 1 | AXI4 Slave | Generic cache port |
S_AXI_CTRL | AXI4-Lite Slave | Control port |
CXS0_RX | CXS Receive | CXS interface |
CXS0_TX | CXS Transmit | CXS Interface |
CQ_AXIS | AXI4-Stream Slave | ATS CQ Interface |
CC_AXIS | AXI4-Stream Master | ATS CC Interface |
RC_AXIS | AXI4-Stream Slave | ATS RC Interface |
RQ_AXIS | AXI4-Stream Master | ATS RQ Interface |
Interrupt | Output | Control interrupt output |
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CHI Port Descriptions
The block diagram of the System Cache core configured for CHI is shown in
the following figure. All interfaces are compliant to AXI4, AXI4-Stream or CHI where applicable. The input signals ACLK
and ARESETN
implement
clock and reset for the entire System Cache core. The M0_CHI interface contains all 6
channels and the separate signals to handle link and system coherency handshake.
Figure 2. CHI Block Diagram
Name | Type | Description |
---|---|---|
ACLK | Input | Core clock |
ARESETN | Input | Synchronous reset of core |
Initializing | Output | Core is initializing after reset |
Sx_AXI_GEN 1 | AXI4 Slave | Generic cache port |
S_AXI_CTRL | AXI4-Lite Slave | Control port |
M0_CHI | CHI | CHI Interface containing all 6 channels and extra signals |
CQ_AXIS | AXI4-Stream Slave | ATS CQ Interface |
CC_AXIS | AXI4-Stream Master | ATS CC Interface |
RC_AXIS | AXI4-Stream Slave | ATS RC Interface |
RQ_AXIS | AXI4-Stream Master | ATS RQ Interface |
Interrupt | Output | Control interrupt output |
|
AXI4/ACE Port Descriptions
The block diagram for the System Cache core is shown in the following figure. All System Cache core interfaces are compliant with AXI4. The input signalsACLK
and ARESETN
implement clock and reset for the entire System Cache
core.Figure 3. AXI/ACE Block Diagram
Name | Type | Description |
---|---|---|
ACLK | Input | Core clock |
ARESETN | Input | Synchronous reset of core |
Initializing | Output | Core is initializing after reset |
Sx_AXI 1 , 2 | AXI4 Slave | MicroBlaze optimized cache port |
Sx_ACE 1 , 2 | ACE Slave | MicroBlaze optimized cache coherent port |
Sx_AXI_GEN 1 | AXI4 Slave | Generic cache port |
M0_AXI 3 | AXI4 Master | Memory controller master port |
M0_ACE 3 | ACE Master | Master interface to ACE port on PS |
S_AXI_CTRL | AXI4-Lite Slave | Control port |
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