The bit assignments for the XIP Status Register (XIP-SR) are shown in This Figure and described in Table: XIP Status Register Description (Core Base Address+0x64). This register is used to check the status of commands and other processes performed by the core. In the case where the core receives write commands or write transactions, an error is generated and this is indicated in the status register. This is a read-only register. Any attempt to write to this register completes with a standard acknowledge and the register contents are not updated. The contents of this register are reset as soon as it is read. As there is no timeout counter involved in the core, if the AXI4 transaction is not accepted, check the status registers for any errors. If there are errors, the core does not accept the AXI4 transaction.
