The AXI Quad SPI core supports AXI4 interface in Enhanced mode and in XIP mode.
- In Enhanced mode, only FIXED AXI4 transactions are allowed for Data Transmit and Data Receive FIFO locations. Any other AXI4 transaction is not allowed and core behavior is not guaranteed.
- In XIP mode, all AXI4 transactions are allowed. It is recommended that you use 32-bit AXI4 transactions. The following points cover further debug information.