Required Constraints - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

The system-level constraints mentioned in Constraining the IP section have to be added in the top XDC files. The numbers mentioned are arbitrary values and update them according to your design.

STARTUP is enabled: The frequency of operation of AXI-QSPI is affected when a STARTUP primitive is enabled. This primitive has its own delay that is not accounted in the entire implementation/timing process.

The STARTUPE2 primitive is used to drive the SCK on the CCLK pin and the STARTUPE3 primitive is used to drive the SCK and data pins.

When using the STARTUP primitive, the clock-data relationship changes due to the extra delay added in the SCK path. This delay can vary from as low as 0.1 ns to as high as 7.5 ns based on the device and speed grade. This value can be found in the FPGA data sheet.

Because this delay is not timed by the tool, you must consider the maximum delay for all calculations. Assume this delay is called CCLK_DELAY. For K7-2 this value can range from
0.5 ns to 6.7ns. This puts the first restriction on the frequency of the clock. The frequency of operation cannot exceed Fmax1 = (1/CCLK_DELAY) MHz