The SPI Data Transmit Register
(SPI DTR) is written with the data to be transmitted on the SPI
bus. After the SPE bit is set to 1 in master mode or spisel is active in the slave mode, the data
is transferred from the SPI DTR to the shift register.
The SPI DTR should be in reset state before filling so that the DTR FIFO write pointer is pointing to the 0th location.